Automatic Frequency Calibration Research Articles

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

This paper presents a charge-pump phase-locked loop (PLL) frequency-synthesizer-based low-jitter wideband clock generator for multi-protocol data communications applications. Automatic frequency calibration (AFC) using linear variable time window technology and modified multi-modulus dividers (MMD) based on sub-multi-modulus dividers (SMMD) are developed for faster locking, lower jitter, and implementation of multi-protocol data communications applications. The clock generator is fabricated in 0.18 μm CMOS technology. The measured division ratio of the multi-modulus divider ranges from 1.875 to 25, and the output frequency is 46.875~625 MHz. The lock time does not exceed 30 μs, while jitter is less than 500 fs.

A radiation tolerant clock generator for the CMS endcap timing layer readout chip

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear Energy Transfer (LET) from 1.3 to 62.5 MeV × cm2/mg.

Fast automatic frequency calibration assisted phase-locked highly stable optoelectronic oscillator

Highly stable, low phase noise microwave oscillators are essential for various applications. An optoelectronic oscillator (OEO) can overcome the short-term phase noise limitation of pure electronic oscillators at high oscillation frequency. Nonetheless, the long-term frequency stability should be addressed. To stabilize the frequency of OEO, a phase-locked loop (PLL) is widely used to synchronize the OEO to a stable reference. However, due to the narrow free-spectral-range (FSR) of the oscillation cavity of the OEO, the pull-in range of the PLL is limited. It is challenging to acquire phase-locking at startup and phase-relocking when mode-hopping of OEO occurs. Here, by using an automatic frequency calibration (AFC) assisted PLL, we attain a highly stable 10 GHz phase-locked OEO with robust phase-locking at startup and phase-relocking when mode-hopping of OEO occurs, for the first time. With the use of a fast digitally-controlled frequency shifter and a real-time frequency error detection unit in the AFC loop, the phase-locking and phase-relocking time are below 120 ms. Furthermore, it shows the phase noise of -135 dBc/Hz at 10 kHz offset, side-mode suppression ratio (SMSR) of 128 dBc, and Allan deviation of 4.8×10-11 at 5000 s for the phase-locked OEO. We thoroughly investigate the dynamics of the automatic frequency calibration, the phase-locking process, the phase-relocking after OEO mode-hopping, the system under vibration, and the frequency switching. Our approach is promising to generate a highly stable, low phase noise, and determinate frequency microwave signal, which can be used as a low phase noise reference for a microwave frequency synthesizer and high performance sampling clock for a data conversion system.

A Bluetooth 5 Transceiver With a Phase-Tracking RX and Its Corresponding Digital Baseband in 40-nm CMOS

A 0.8-V Bluetooth 5 (BT5) digitally intensive transceiver with a phase-tracking RX and a digital TX in 40-nm CMOS is presented. For the phase-tracking RX, a hybrid loop filter with a loop-delay compensation is proposed to suppress digitally controlled oscillator (DCO) sidelobe energy, enhancing interference resilience. To facilitate the DCO-based phase-tracking RX for the reception of BT5 signals, a corresponding digital baseband is implemented with a carrier frequency offset (CFO) calibration to remove the initial static CFO error during the preamble, while an automatic frequency calibration tackles the frequency drift during the payload. An all-digital phase-locked loop (ADPLL)-based digital frequency-modulation (FM) interface shared between TX and RX provides a precise deviation frequency control, ensuring the quality of signal transmission and reception. In the RX mode, the chip consumes 2.3 mW from a 0.8-V supply, achieving a figure of merit (FoM) of 180 dB with −91-/−94-dBm sensitivity at 2/1 Mb/s. In the TX mode, it consumes 6.1 mW when delivering a maximum 1.8-dBm output power, resulting in 25% TX system efficiency.

A 0.045- to 2.5-GHz Frequency Synthesizer With TDC-Based AFC and Phase Switching Multi-Modulus Divider

A 0.045- to 2.5- GHz wideband frequency synthesizer (FS) employing time-to-digital converter (TDC) based automatic frequency calibration (AFC) method and phase switching (PS) multi-modulus divider (MMD) is presented in this paper. The traditional counter-based AFC method takes several reference cycles to calculate the instantaneous voltage-controlled oscillator (VCO) frequency, while the proposed TDC-based technique consumes only 2 cycles. In order to suppress the quantization noise caused by the sigma-delta modulator (SDM) in the MMD, the loop division step is reduced from 2 to 0.5 by adopting the PS technique. The FS is designed and implemented using TSMC 180nm RF CMOS process and provides the phase noise performance of −99.5 / −123.5 dBc/Hz at 10kHz/1MHz offsets under 2.4 GHz carrier frequency. The AFC time measurement results for a 6-bit cap-array are 1.25-, 2.5- and 5- $\mathrm {\mu s}$ when employing 48-, 24- and 12-MHz reference frequencies respectively. The chip area including pads and I/Os is 2.31 mm $^{\mathbf {2}}$ and the total power consumption is 108 mW.

A Fully Integrated 0.27-THz Injection-Locked Frequency Synthesizer With Frequency-Tracking Loop in 65-nm CMOS

A fully integrated sub-terahertz (sub-THz) frequency synthesizer is proposed cascading a radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection-locked frequency multipliers (ILFMs) and a sub-THz mixer for frequency extension. Enhanced third-harmonic and fourth-harmonic-extraction techniques are proposed for the ILFMs with different multiplication ratios. In addition, a frequency-tracking loop (FTL) with automatic frequency and amplitude calibration is embedded for the ILFMs. Finally, a distributed bias technique is employed to improve the linearity of the wideband magnetic-tuning sub-THz oscillator. Designed in a 65-nm CMOS process, the proposed prototype achieves an ultra-wide frequency tuning range from 61.2 to 100.8, 122.4 to 136.8, and 198.5 to 273.6 GHz with a phase noise at 1-MHz offset from -79.3 to -95.4 dBc/Hz and an integrated jitter from 124 to 159 fs over the tuning range. The synthesizer occupies a core area of 0.58 mm2 and measures an output power of -11 dBm at 211.4 GHz with 49.5 mW, corresponding to a dc-to-radio frequency (RF) efficiency of 0.16%, an FoM from -171.4 to -177.7 dBc/Hz, and FoMT from -177 to -190.5 dBc/Hz.

Auto-Resonant Tuning for Capacitive Power and Data Telemetry Using Flexible Patches

This brief proposes and demonstrates a reliable power and data transfer scheme for biomedical implants through a resonant capacitive link. Flexible, conformable, and biocompatible patches are adopted with an automatic resonant frequency calibration technique for the first time. A voltage feedback network, a Class- ${D}$ driver, and a custom algorithm have been developed for the low overhead calibration. An ex vivo chicken skin tissue-based experiment with 4 cm2 flexible, conformal capacitive patches demonstrated the method. Experimental results show that the power delivered to the load (PDL) of the link extends up to 150 mW and maximum power transfer efficiency (PTE) of the link is 54%. A simultaneous data transfer with a rate of up to 170 kbps alongside power transfer using 1.5 to 2 mm-thick biological skin tissue has been achieved.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A CMOS MedRadio Transceiver With Supply-Modulated Power Saving Technique for an Implantable Brain–Machine Interface System

A MedRadio 413–419-MHz inductorless transceiver (TRX) for an implantable brain–machine interface (BMI) in a 180 nm-CMOS process is presented. Occupying 5.29 mm2 of die area (including pad ring), this on–off keying (OOK) TRX employs a non-coherent direct-detection receiver (RX), which exhibits a measured in-band noise figure (NF) of 4.9 dB and $S_{11}$ of −13.5 dB. An event-driven supply modulation (EDSM) technique is introduced to dramatically lower the RX power consumption. Incorporating an adaptive feedback loop, this RX consumes 42-/92- $\mu \text{W}$ power from 1.8-V supply at 1/10-kbps data rates, achieving −79/−74-dBm sensitivities for 0.1% bit error rate (BER). The TX employs a current starved ring oscillator with an automatic frequency calibration loop, covering 9% supply voltage variation and 15 °C–78 °C temperature range that guarantees operation within the emission mask. The direct-modulation TX achieves 14% efficiency for a random OOK data sequence at −4-dBm output power. Wireless testing over a 350-cm distance accounting for bio-signal data transfer, multi-user coexistence, and in vitro phantom measurement results is demonstrated.

An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS

An interference-robust reconfigurable receiver in 65-nm CMOS is presented. The front end is split into a low-band (LB) RF path (0.1–1.5 GHz) and a high-band (HB) RF path (1–5 GHz). By utilizing a harmonic recombination technique, the LB path could reject the third /fifth-order harmonic interferences. A tunable narrowband dual-feedback common-gate low-noise amplifier (LNA) with $LC$ resonant load provides second-order bandpass filtering to reject the harmonic interferences in the HB path. The RF high-Q bandpass filtering based on the voltage-mode passive mixer and the current-mode low-pass filter in the analog baseband improves the receiver’s resilience to out-of-band interferences. A novel power-detection-based automatic frequency calibration technique is proposed to calibrate the operating frequency of the LNA in the HB path and overcome the effects of process, voltage, and temperature variations. The presented receiver has been implemented in a 65-nm CMOS and consumes 20–76-mW power from 1.2-V power supplies, with a core die area of 5 mm2. The measured results show that the receiver can tolerate −5-dBm interference with 16-dB noise figure (NF) and achieve 95–105-dB maximum conversion gain and 1.7–8-dB NF over 0.1–5 GHz. It also achieves an average harmonic rejection (HR3)/HR5 of 61/68-dB, +7.1/+14.4 dBm in-band/out-of-band input third-order intercept point (OB-IIP3), +71.2-dBm OB-IIP2, and 58.1-dB-image rejection, after the digitally assisted calibrations. The system-level measurements show that the presented receiver achieves 2.1% error vector magnitude (EVM) for 850-MHz Global System for Mobile Communication signals and 5% EVM for band 42 time division duplexing-local thermal equilibrium (LTE) signals, respectively.

Short-Range Low-Data-Rate FM-UWB Transceivers: Overview, Analysis, and Design

This paper summarizes and compares various circuit configurations of sub-modules and RF front-ends for frequency modulated ultra-wideband (FM-UWB), and analyzes the transceiver design parameters and link margin. High-robust relaxation oscillator for subcarrier generation, low-power ring oscillators for RF FM, automatic frequency calibration (AFC) for system robustness, and preamplifier-latch based analog phase interpolation for FM demodulation, are specially clarified. A prototype 3.6–4.1 GHz FM-UWB system with bowtie antennas for short-range low-data-rate wireless data transmission is implemented in 0.18- $\mu\text{m}$ CMOS. Experimental results show that the presented FM-UWB transceiver successfully generates FCC-compliant UWB spectrum and demodulates the dual-FM information, with a bit error rate (BER) of $10^{-6}$ at a distance of 60 cm and with an energy efficiency of 185 nJ/bit.

Reconfigurable All-Band RF CMOS Transceiver for GPS/GLONASS/Galileo/Beidou With Digitally Assisted Calibration

This paper presents a fully integrated reconfigurable all-band RF transceiver for GPS/GLONASS/ Galileo/Beidou in 55-nm CMOS. The transceiver incorporates three low-IF receivers (RXs) and one direct up-conversion BPSK transmitter (TX), which can be configured to receive any two global navigation satellite system (GNSS) signals or switched to process the Chinese Beidou(I) signals. A switching module is integrated to provide the connectivity between different RF front-end and IF channel (IFC), which will effectively simplify the design complexity of the IFC and save power consumption, while the GNSS signals are received. A flexible frequency plan with two frequency synthesizers is utilized to satisfy different local oscillator requirements of the transceiver. An optimized automatic frequency calibration scheme using an error compensation logic enables fast and high-precision calibration process for optimum phase-locked loop operation. Several digitally assisted calibration modules are integrated to ensure that the chip performance only shows a weak process, voltage and temperature (PVT) dependence. While drawing about 21.5–30.2 mA per RX channel from a 1.2-V supply, the RXs achieve an image rejection ratio more than 49 dB after I/Q mismatch calibration, an automatic gain control range of 88 dB, and an input-referred 1 dB compression point of better than −25 dBm with a minimum noise figure of about 2 dB. The output power of the TX is about 5 dBm with about 6% error vector magnitude (EVM) and 30-mA current from a 1.2-V supply. The whole transceiver consumes a die area of $2.8 \times 3~{\rm mm}^{2}$ .

A Wide-Locking-Range Dual Injection-Locked Frequency Divider With an Automatic Frequency Calibration Loop in 65-nm CMOS

This brief presents a wide-locking-range injection-locked frequency divider (ILFD) that uses an automatic frequency calibration loop. The proposed ILFD uses the ring oscillator to provide the high division ratio with small chip area. A dual-injection scheme is proposed in order to achieve the wide locking range of the ILFD. The free-running frequency of the ILFD is automatically digitally calibrated to reflect the frequency of the injected signal from the voltage-controlled oscillator. To control the frequency of the ILFD, the load current is digitally tuned with 3-bit control signal. The ILFD is fabricated using 65-nm CMOS process, and by tuning the load current, it achieves the wide operation frequency range of 14.1-45.8 GHz. When the input signal of 30 GHz is injected, the locking range of the ILFD is 7.2 GHz, while the power consumption is 2.5 mW from a 1-V supply voltage.

Low noise frequency synthesizer with self-calibrated voltage controlled oscillator and accurate AFC algorithm

A low noise phase locked loop (PLL) frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75–11.5 GHz high frequency wide band local oscillator (LO) carriers. Tested 11.5 GHz LO bears a phase noise of−104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm2, including bias circuits and buffers.

A 0.4-V, 90 <inline-formula> <tex-math notation="TeX">$\sim$</tex-math></inline-formula> 350-MHz PLL With an Active Loop-Filter Charge Pump

A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.

A time-to-digital converter based AFC for wideband frequency synthesizer

The automatic frequency calibration (AFC) technique is routinely used in wideband frequency synthesizers that contain multiple voltage-controlled oscillator (VCO) tuning curves. In this paper, a counter-based AFC that uses a time-to-digital converter (TDC) in the counting process is developed. The TDC is able to capture the fractional VCO cycle information within the counting window. This significantly improves the frequency detection accuracy over the existing counter-based AFC techniques. In addition, a quantitative model is developed to determine the minimally required error-free AFC calibration time for a given VCO tuning curve characteristic. An AFC circuit using the proposed TDC-based counter is designed in a 0.13-μm CMOS technology. Simulation results show that the proposed AFC significantly improves the frequency detection accuracy and consequently for a given frequency detection resolution reduces the AFC calibration time. The simulated error-free AFC time is <2.5 μs with a frequency resolution of 0.04 %.

A tunable Gm-C polyphase filter with high linearity and automatic frequency calibration

A tunable Gm-C polyphase filter with high linearity and automatic frequency calibration

A fast and efficient automatic frequency calibration technique for 10 GHz PLLs

A fast and efficient automatic frequency calibration technique for 10 GHz PLLs

A Continuously and Widely Tunable 5 dB-NF 89.5 dB-Gain 85.5 dB-DR CMOS TV Receiver With Digitally-Assisted Calibration for Multi-Standard DBS Applications

This paper presents a direct-conversion, multi-standard TV receiver implemented in a 0.13 μm CMOS technology occupying less than 4 mm2. The receiver is compliant with several direct broadcasting satellite (DBS) standards, including DVB-S, DVB-S2, and ABS-S. A novel automatic frequency tuning (AFT) technique is adopted based on a searching algorithm to ensure less than 6% bandwidth deviation of the different bandwidths (over 40 bandwidth channels) for multi-standard applications. Moreover, digitally-assisted DC offset calibration is used to improve second-order distortion and calibration time of the receiver and the residual output offset achieved is less than 3 mV. An integrated ΣΔ fractional-N synthesizer utilizing an optimized automatic frequency calibration (AFC) scheme enables a fast and high-precision calibration process for dual-VCO phase-locked loop (PLL) operation. The measured linearity exceeds the desired target with the minimum margin in excess of 7 dBm, and the maximum carrier-to-noise ratio (CNR) values are better than 30 dB over wide input power levels, ensuring robust reception in variable environments. All circuit blocks are operated at 2.8 V stabilized by an LDO and consuming a total current of about 56 mA.

A Low-Power Fast-Settling Bond-Wire Frequency Synthesizer With a Dynamic-Bandwidth Scheme

This paper presents a low-power fast-settling phase-locked loop (PLL) frequency synthesizer working at 1.72–1.74 GHz for a 100 kb/s Gaussian frequency shift keying (GFSK) based transceiver suitable for wireless sensor network (WSN) applications. We propose several new techniques for lowering the power consumption in the frequency synthesizer. Resistor-based electro-static discharge protection (ESD-P) and automatic frequency calibration (AFC) are introduced to the bond-wire voltage-controlled oscillator (VCO) to deal with the inaccuracy of bond-wire inductors and uncertain parasitics. A multi-stage power-scaling scheme is developed for classical phase-switching prescaler. A dynamic-bandwidth scheme is proposed to speed up the settling time and improve the energy efficiency in a time-division WSN system. Implemented in 0.18 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS technology, the measurement results show that the PLL consumes 10.6 mW under 1.8 V supply voltage and settles within 18 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu{\hbox {s}}$</tex></formula> including the AFC process. The phase noise is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 89.8 dBc/Hz@10 kHz and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 119.3 dBc/Hz@1 MHz under receiving (Rx) mode; from receiving (Rx) state to transmitting (Tx) state, the out-band fractional- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$N$</tex></formula> phase noise is increased by 2.7 dB, whereas the in-band noise is lowered by 2.1 dB.