Automatic Test Equipment System Research Articles

A 93.4-dB SNDR single-ended SAR ADC with a hybrid R–C DAC

In highly-integrated automatic test equipment (ATE) systems, the quantization process of single-ended analog signals demands high-precision ADCs. This paper presents a high precision single-ended SAR ADC with a hybrid R–C DAC. The proposed SAR ADC is demonstrated through sequential modeling in MATLAB, pre-layout and post-layout simulation. Designed in 0.18 μm BCD process, the post-layout simulation results show that it achieves a peak SNDR of 93.4-dB, a peak SFDR of 98.6-dB with a 250 kHz bandwidth. The power consumption of this SAR ADC is 5.96 mW with 5V supply. The Schreier Figure-of Merit (FoMSNDR) is 169.6-dB. The presented ADC is suitable for low-speed, high-precision ATE systems.

Automated configuration of modern ATE

Modern Automatic Test Equipment (ATE) must perform many tasks to support testing of devices. The devices being tested may be anything from simple circuit cards to complex multi-device systems. In addition, they may employ analog, digital and / or radio frequency testing. This, coupled with the desire to test the devices as quickly as possible, can drive ATE systems to employ multiple systems with their own associated computers in order to perform complex testing in as short a time as possible. Another requirement of modern ATE is that they are able to be quickly repaired and be able to be configured quickly to perform their intended function. Since the platforms on which the tested equipment is installed cannot be used unless they are completely operational, the ATE used to test that equipment must be available to perform the testing. Additionally, it is often intended that the testing and repair tasks be performed by non-technical or semi-technical individuals. It is this last capability that can drive the desire to support the ability to perform automated installation and configuration of the ATE systems.

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing

This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT), and demonstrates its effectiveness for eliminating the overkills/underkills due to the difference of power supply impedance between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method injects compensation currents into the power supply nodes on the ATE system in a feed-forward manner such that the ATE power supply waveform matches with the one on the customer's operating environment of the DUT. A method for calculating the compensation current is also described. Experimental results show that the proposed method can emulate the power supply voltage waveform under a customer's operating condition and eliminate 95 % of overkills/underkills in the maximum operating frequency testing with 105 real silicon devices. Limitations and applications of the proposed method are also discussed.

Demodulation Test for WCDMA RF-SOC in ATE

Today more and more chips include most complex combining RF/IF functions with digital, analog and DSP functions, which are called System-on-chip (SOC). Usually, these consuming SOCs are electrically test with Automatic Test Equipment (ATE). In test strategies, error vector magnitude (EVM) is often used to evaluate the actual ability of SOC device to perform properly in the system. In this paper, brief introduction to EVM test is given, and test methodologies in ATE system V93000 is introduces. A new test method for EVM using equalization function to optimize RF source signal is proposed to compensate interference in test system. Using this method, device performance is better characterized and also improves the yield in production test.

An Integrated Environment for Design Verification of ATE Systems

This paper deals with the verification of automatic test equipment (ATE) that is widely used for manufacturing testing of integrated circuits (ICs). Due to design complexity, manufacturers are facing substantial difficulties in verifying ATEs. Design flow and time execution of the verification process are severely limited when developing new hardware and software architectures for ATEs. We present a verification technique and its implementation, which has been put in practice in an ATE company. This technique reduces the time to detect errors in incorrect designs and provides an inexpensive and practical approach to verification of ATEs. It is based on establishing an integrated environment for the concurrent execution of diagnostic programs (which are developed for postmanufacturing ATE diagnosis) and the hardware- description-language models of the units of the ATE. Experimental results are provided to verify an application-specific IC chip for test pattern generation in the test head and software of the ATE.

Rack-and-stack instruments: often a better choice than VXI or PXI systems

Automatic test equipment systems made of mature and robust precision instruments tied together with proven interfaces such as GPIB and Ethernet can provide equal or higher value, lower cost of ownership with much better reliability than backplane-based systems. GPIB (general purpose interface bus) allows for complete computer control of all the instruments in the system using easy-to-learn SCPI (standard commands for programmable instrumentation) programming. Ethernet also gives a lot of flexibility for data networking and databasing and, more recently direct instrument control.

The benefits of using ATE systems in the testing of printed circuit boards

An industry-based pragmatic review is provided of the economic and product-quality consequences of automatic test equipment (ATE) usage in printed circuit board testing. The company selection process, the nature of the industrial participants, and the data collection process are described. The benefits obtained by users are identified. It is demonstrated that the use of ATE systems does result in definable economic and quality-level benefits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Achieving Accurate Timing Measurements on TTL/CMOS Devices

Production TTL and CMOS timing measurements obtained between different test systems and between test systems and the bench setup often do not correlate or do not appear to be accurate even though the automatic test equipment system has subnanosecond accuracy. Errors of as much as 2 ns can occur with small-, medium-, and large-scale integration and with gate arrays using the new TTL and CMOS technologies. This represents a 100- percent error factor for these emerging products.

Design for testability

Testing of circuits with a few hundred logic functions can, in general be performed by the use of selected logic stimuli (Mueldorf and Savkav (1)). Exhaustive testing of circuits demands that all possible logic states in which a circuit can exist must be considered. Automatic test pattern generation (ATPG) methods (Williams and Parker (2), Papaionnou (3), Schnurmann et al (4)) can be used to effect in determining the test stimuli (or test vectors) required to achieve or approximate such an exhaustive test. For combinational circuits where the present states of the output variables are a function only of the present states of the input variables, exhaustive testing requires derivation of a test sequence to create all of the possible input combinations and check the outputs for correct responses. These input stimuli can be applied from automatic test equipment systems (ATE) and the responses can subsequently be sensed by the same equipment.

A Synthesis Technique for Networks Consisting of Logical Functions Feeding a Linear Summation Element

Compiler programs are used to convert engineering test specifications to a digital code which can be interpreted by the automatic test equipment system. A programming language based upon decision-table techniques allows the test engineer to write his test statements in an extremely convenient fashion and permits him to program any test specification with only a minimum of knowledge about the specific test equipment system and particular programming techniques.

Using a Decision-Table Structure as the Input Language Format for Programming Automatic Test Equipment Systems

Compiler programs are used to convert engineering test specifications to a digital code which can be interpreted by the automatic test equipment system. A programming language based upon decisiontable techniques allows the test engineer to write his test statements in an extremely convenient fashion and permits him to program any test specification with only a minimum of knowledge about the specific test equipment system and particular programming techniques.

An Application of Decision Tables as the Source Language for Automatic Testing

This paper presents a source language based upon decision tables for applications involving automatic test equipment systems. The method described allows the engineer to state his test requirements in an extremely convenient fashion, and permits him to program any test specification directly using engineering terminology. Only a minimum of knowledge about the specific test equipment system and particular programming techniques is required as a background. This method enhances the ability of the engineer to program any automatic test equipment system and reduces long-term programming expenses.

Research Guidelines for Digital Computer-Controlled Systems for Checkout and Fault Isolation

The past decade has seen a tremendous increase in the complexity and capability of aerospace and weapons systems. However maintenance philosophy and checkout procedures have not kept pace. The maintenance procedures have been evolving slowly through three major phases: a. Manual Maintenance Procedures b. Serially Programmed Automatic Test Equipment c. Computer-Controlled Automatic Test Equipment In the latter case a small but highly capable general-purpose digital computer is used as the controller for the Automatic Test Equipment. Once a general standardized programmed set of stimuli and measuring instruments is incorporated in a computer-controlled automatic test system, one need only modify the program in the Automatic Test Equipment system memory rather than develop a new set of test equipment for each new system under test. Much of the basic feasibility work has already been completed for such computer controlled Automatic Test Equipment. This is summarized along with discussion of remaining problem areas. Of especial importance is the dependence of program details on the level of tests to be performed; e.g. overall system checkout or isolation of fault to subsystem, assembly, chassis, module, or component. It is shown that while the program details differ, the same test philosophy can be applied.