An Integrated Environment for Design Verification of ATE Systems

Abstract

This paper deals with the verification of automatic test equipment (ATE) that is widely used for manufacturing testing of integrated circuits (ICs). Due to design complexity, manufacturers are facing substantial difficulties in verifying ATEs. Design flow and time execution of the verification process are severely limited when developing new hardware and software architectures for ATEs. We present a verification technique and its implementation, which has been put in practice in an ATE company. This technique reduces the time to detect errors in incorrect designs and provides an inexpensive and practical approach to verification of ATEs. It is based on establishing an integrated environment for the concurrent execution of diagnostic programs (which are developed for postmanufacturing ATE diagnosis) and the hardware- description-language models of the units of the ATE. Experimental results are provided to verify an application-specific IC chip for test pattern generation in the test head and software of the ATE.