Automatic Design Space Exploration Research Articles

Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend

The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of an HDL-description into a corresponding circuit. This paper presents a method for behavioral synthesis of asynchronous circuits which builds on top of syntax directed translation, and which allows the designer to perform automatic design space exploration guided by area or speed constraints. This paper presents an asynchronous implementation template consisting of a data-path and a control unit and its implementation using the asynchronous hardware description language Balsa. This ldquoconventionalrdquo template architecture allows us to adapt traditional synchronous synthesis techniques for resource sharing, scheduling, binding, etc., to the domain of asynchronous circuits. A prototype tool has been implemented on top of the Balsa framework, and the method is illustrated through the implementation of a set of example circuits. The main contributions of this paper are the fundamental idea, the template architecture and its implementation using asynchronous handshake components, and the implementation of a prototype tool.

Automated Design Space Exploration for DSP Applications

We present a performance analysis framework that efficiently generates and analyzes hardware designs for computationally intensive signal processing applications. Our framework synthesizes designs from a high level of abstraction into well-constructed and recognizable hardware structures that perform well in terms of area, throughput and power dissipation. Cost functions provided by our framework allow the user to reduce the design space to a set of efficient hardware implementations that meet performance constraints. We utilize our framework to estimate hardware performance using a set of pre-synthesized mathematical cores which expedites the synthesis process by approximately 14 fold. This reduces the architectural generation and hardware synthesis process from days to several hours for complex designs. Our work aims at performing hardware optimizations at the architectural and arithmetic levels, relieving the user from manually describing the designs at the register transfer level and iteratively varying the hardware structures. We illustrate the efficiency and accuracy of our framework by generating finite impulse response filter structures used in several signal processing applications such as adaptive equalizers and quadrature mirror filters. The results show that hardware filter structures generated by our framework can achieve, on average, a 3 fold increase in power efficiency when compared to manually constructed designs.

Evaluating the model accuracy in automated design space exploration

Design space exploration is used to shorten the design time of system-on-chips (SoCs). Exploration uses abstracted system models that need to be both accurate and fast to simulate. This paper introduces a multi-level communication cost to improve the accuracy of the abstracted models. During the simulation, one of three different communication costs is applied for each inter-task communication event based on the mapping of the communicating tasks. The accuracy of three system abstraction models using the presented communication cost is evaluated with a Motion-JPEG application in a multi-processor SoC with 9 mappings having 1–4 processors. The application is described in Unified Modeling Language (UML) and simulated using transaction generator (TG) simulation engine. According to the results, the average error in frames per second is 4.3% for the modulo model, 5.0% for the trace model, and 12.8% for the probabilistic model compared to FPGA execution. The simulation speed-up is more than 230× compared to low-level cycle-accurate simulation. The results show that with the multi-level communication cost the accuracy is increased significantly without sacrificing the simulation speed.

Automatic Design Space Exploration of Register Bypasses in Embedded Processors

Register bypassing is a popular and powerful architectural feature to improve processor performance in pipelined processors by eliminating certain data hazards. However, extensive bypassing comes with a significant impact on cycle time, area, and power consumption of the processor. Recent research therefore advocates the use of partial bypassing in a processor. However, accurate performance evaluation of partially bypassed processors is still a challenge, primarily due to the lack of bypass-sensitive retargetable compilation techniques. No existing partial bypass exploration framework estimates the power and area overhead of partial bypassing. As a result, the designers end up making suboptimal design decisions during the exploration of partial bypass design space. This paper presents PBExplore - an automatic design-space-exploration framework for register bypasses. PBExplore accurately evaluates the performance of a partially bypassed processor using a bypass-sensitive compilation technique. It synthesizes the bypass control logic and estimates the area and energy overhead of each bypass configuration. PBExplore is thus able to effectively perform multidimensional exploration of the partial bypass design space. We present experimental results of benchmarks from the MiBench suite on the Intel XScale architecture on and demonstrate the need, utility, and exploration capabilities of PBExplore.

Embedded Digital Signal Processing Systems

With continuing progress in VLSI and ASIC technologies, digital signal processing (DSP) algorithms have continued to find great use in increasingly wide application areas. DSP has gained popularity also in embedded systems although these systems set challenging constraints for implementations. Embedded systems contain limited resources, thus embedded DSP systems must balance tradeoffs between the requirements on computational power and computational resources. Energy efficiency has been important in batterypowered devices, but nowadays also the limited heat dissipation in small devices calls for low-power consumption. Successful implementation of DSP applications in embedded systems requires tailoring, which in turn sets challenges for design methodologies. For this special issue, we received 14 submissions and a collection of seven papers was finally accepted. The special issue is opened by “Observations on power-efficiency trends in mobile communication devices,” where the authors O. Silven and K. Jyrkka analyze the power consumption in the current mobile communication devices. Several bottlenecks in the current implementation style have been identified, thus the paper provides a good motivation for the following papers. In “The Sandbridge SB3011 platform,” the authors John Glossner et al. describe a system-on-a-chip (SoC) multiprocessor targeted as a software-defined radio platform. The platform provides solutions to the challenges in future mobile devices given in the previous paper. “A shared memory module for asynchronous arrays of processors” authored byMichael J. Meeuwsen et al. considers also chip multiprocessors. The presented shared memory module can be used for interprocess communication or to increase application performance by parallelizing computation. In “Implementing a WLAN video terminal using UML and fully automated design flow” by Petri Kukkala et al., an automated design flow for multiprocessor SoC is presented. The flow is based on UML descriptions and the authors demonstrate their design flow with a design case. Programming of chip multiprocessor platforms is considered in “pn: a tool for improved derivation of process networks” by Sven Verdoolaege et al. The paper discusses conversion of sequential programs to process networks allowing optimization of communication channels and buffers. In “A SystemC-based design methodology for digital signal processing systems,” the authors Christian Haubelt et al. describe a design flow for SoC designs containing automatic design space exploration, performance evaluation, and automatic platform-based system generation. The design flow is based on SystemC descriptions and the presented tools can automatically detect the underlying model of computation. Application-specific implementations are often used to speedup certain DSP tasks in embedded systems. In “Priority-based heading one detector in H.264/AVC decoding,” the authors Ke Xu et al. consider such implementations to speed up video decoding applications. The authors present a low-power decoder implementation for context-adaptive variable length coding defined in H.264 standard.

A SystemC-Based Design Methodology for Digital Signal Processing Systems

Digital signal processing algorithms are of big importance in many embedded systems. Due to complexity reasons and due to the restrictions imposed on the implementations, new design methodologies are needed. In this paper, we present a System C-based solution supporting automatic design space exploration, automatic performance evaluation, as well as automatic system generation for mixed hardware/software solutions mapped onto FPGA-based platforms. Our proposed hardware/software codesign approach is based on a System C-based library called SysteMoC that permits the expression of different models of computation well known in the domain of digital signal processing. It combines the advantages of executability and analyzability of many important models of computation that can be expressed in SysteMoC. We will use the example of an MPEG-4 decoder throughout this paper to introduce our novel methodology. Results from a five-dimensional design space exploration and from automatically mapping parts of the MPEG-4 decoder onto a Xilinx FPGA platform will demonstrate the effectiveness of our approach.

HIBI Communication Network for System-on-Chip

This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates.HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μ m technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals.Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration.

Improving Automatic Design Space Exploration by Integrating Symbolic Techniques into Multi-Objective Evolutionary Algorithms

Solving Multi-objective Combinatorial Optimization Problems (MCOPs) is often a twofold problem: Firstly, the feasible region has to be identified in order to, secondly, im- prove the set of non-dominated solutions. In particular, prob- lems where the construction of a single feasible solution is NP - complete are most challenging. In the present paper, we will pro- pose a combination of Multi-Objective Evolutionary Algorithms (MOEAs) with Symbolic Techniques (STs) to solve this problem. Different Symbolic Techniques, such as Binary Decision Dia- grams (BDDs), Multi-valued Decision Diagrams (MDDs), and SAT solvers as known from digital hardware verification will be considered in our methodology. Experimental results from the area of automatic design space exploration of embedded sys- tems illustrate the benefits of our proposed approach. As a key result, the integration of STs in MOEAs is particularly useful in the presence of large search spaces containing only few feasible solutions.