Automatic Design Space Exploration Research Articles

Automated Pipe Design in 3D using a Multi-Objective Toolchain for Efficient Decision-Making

Abstract Pipe design in 3D is typically characterized by competing objectives, since the different design objectives, such as the reduction of length, weight, number of bends, manufacturing cost and overall angle sum, are examples for such competing design goals, where one goal is often at the expense of the other. The origin of these competing design goals lies in the highly coupled problems of finding a permissible and collision-free pipe path in a complex 3D geometry and the physical properties of the path found. Because of the complex physics and geometry, these couplings are highly nonlinear and mostly accessible via simulation only. The underlying pipe design optimization problem can thus not be solved explicitly and is tackled instead with a multi-disciplinary search procedure. Since the trade-offs between different competing evaluation objectives are often not known in advance, an automated design space exploration can be performed to generate different pipe designs, leading to well-informed design decisions by human experts. Such a design space exploration is shown and discussed using the pipework in a mounting rack in an Airbus A320 main landing gear bay. A total of 144 valid designs are generated, out of which the best in each criteria and the pareto-optimal solutions are automatically selected. Compared to the manually created Airbus A320 series solution, up to $10.4\%$ of the pipe length or up to $16.9\%$ of the bends can be saved using the same fixings and connection points, demonstrating both the feasibility and the industrial applicability of the automated toolchain.

HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space Exploration

Coarse-grained reconfigurable arrays (CGRAs) are promising design choices in computation-intensive domains, since they can strike a balance between energy efficiency and flexibility. A typical CGRA comprises processing elements (PEs) that can execute operations in applications and interconnections between them. Nevertheless, most CGRAs suffer from the ineffectiveness of supporting flexible architecture design and solving large-scale mapping problems. To address these challenges, we introduce HierCGRA, a novel framework that integrates hierarchical CGRA modeling, Chisel-based Verilog generation, LLVM-based data flow graph (DFG) generation, DFG mapping, and design space exploration (DSE). With the graph homomorphism (GH) mapping algorithm, HierCGRA achieves a faster mapping speed and higher PE utilization rate compared with the existing state-of-the-art CGRA frameworks. The proposed hierarchical mapping strategy achieves 41× speedup on average compared with the ILP mapping algorithm in CGRA-ME. Furthermore, the automated DSE based on Bayesian optimization achieves a significant performance improvement by the heterogeneity of PEs and interconnections. With these features, HierCGRA enables the agile development for large-scale CGRA and accelerates the process of finding a better CGRA architecture.

SpikeExplorer: Hardware-Oriented Design Space Exploration for Spiking Neural Networks on FPGA

One of today’s main concerns is to bring artificial intelligence capabilities to embedded systems for edge applications. The hardware resources and power consumption required by state-of-the-art models are incompatible with the constrained environments observed in edge systems, such as IoT nodes and wearable devices. Spiking Neural Networks (SNNs) can represent a solution in this sense: inspired by neuroscience, they reach unparalleled power and resource efficiency when run on dedicated hardware accelerators. However, when designing such accelerators, the amount of choices that can be taken is huge. This paper presents SpikExplorer, a modular and flexible Python tool for hardware-oriented Automatic Design Space Exploration to automate the configuration of FPGA accelerators for SNNs. SpikExplorer enables hardware-centric multiobjective optimization, supporting target factors such as accuracy, area, latency, power, and various combinations during the exploration process. The tool searches the optimal network architecture, neuron model, and internal and training parameters leveraging Bayesian optimization, trying to reach the desired constraints imposed by the user. It allows for a straightforward network configuration, providing the full set of explored points for the user to pick the trade-off that best fits their needs. The potential of SpikExplorer is showcased using three benchmark datasets. It reaches 95.8% accuracy on the MNIST dataset, with a power consumption of 180 mW/image and a latency of 0.12 ms/image, making it a powerful tool for automatically optimizing SNNs.

Comparison of Response Surface Based Preliminary Design Methodologies for a Gas Turbine Combustor

Preliminary design of gas turbine combustor is a multi-objective optimization problem. The methodology to be used at the preliminary design stage depends on the freedom of design choices available. In this article, we explore three preliminary design methodologies for gas turbine combustor - M1: combustion liner design for a given casing; M2: combustion liner design without the casing and M3: coupled design of combustion liner and casing. A workflow for the automated design space exploration of gas turbine combustor using response surface methodology is presented. Computational fluid dynamics studies along with central composite design for design of experiments and genetic aggregation for response surface generation are used to quantify the combustor performance in design space. Comparison of three different design methodologies (M1, M2 and M3) is made to show how the choice of design methodology changes the available design space and limits/expands combustor performance. Candidate optimal designs and associated trade-offs from the optimization study are also presented. This study can aid combustor design engineers choose the most suitable preliminary design methodology for their specific use case.

Automated design space exploration for poultry processing systems using discrete-event simulation

Abstract The poultry processing industry struggles to keep up with new developments in meat consumption and livestock breeding. Designing poultry processing systems is becoming increasingly more complex, and an increasing number of iterations of (re)design are required to optimize the product flow in these systems. To address this issue, this study presents a discrete-event simulation-based method for design space exploration of production systems. This method is mostly automated, greatly reducing the time and effort required in the design process. The steps that are automated are iterating on the design, model construction, performing simulation experiments, and interpreting the simulation results. An industrial case study in which a poultry processing system is redesigned is used to validate the effectiveness of the proposed method. A detailed description of this case study is given to showcase the different ways in which this design space exploration method can be used.

TSAR-ILP: Tile-Based, Synchronization-AwaRe ILP Allocating Heterogeneous Platforms for Streaming Applications

Automatic design space exploration (DSE) is key in hardware-software (HW/SW) co-design. To cope with the large design space, explorations are often heuristic-based and/or approximate yielding potentially locally optimal solutions. Without knowing the globally optimal solution, strong assertions about performance upper / lower bounds cannot be made. In contrast, integer linear programming (ILP) formulations can produce exact (optimal) solutions. Previous ILP-based formulations, however, lack support for tile-based architectures and realistic synchronization models, limiting their DSE capabilities. This work introduces a tile-based, synchronization-aware ILP (TSAR-ILP) formulation that overcomes previous limitations. With TSAR-ILP, the allocation / binding problems are introduced and formalized, attaining optimal solutions for mapping streaming applications onto template platforms. Using TSAR-ILP, this work explores a hardware acceleratorrich (HWACC-rich) platform with direct HWACC-to-HWACC communication under HW area constraints for 40 OpenVX applications. To illustrate design opportunities given by (a) the ILP formulation and (b) direct HWACC-to-HWACC communication, this paper analyzes the impact of job size. Results show that selecting smaller job sizes yields performance improvements and less area usage at the cost of slightly increased synchronization overhead. A job size reduction from 1 kB to 256 bytes gives 3.51x average performance increase across 40 applications. Finally, DSE with TSAR-ILP is shown not to be prohibitive through scalability analysis using a set of 5000 synthetic applications with varying size (10-125 nodes), with 94.3% of applications successfully achieving optimal solutions under 60 seconds.

Flydeling: Streamlined Performance Models for Hardware Acceleration of CNNs through System Identification

The introduction of deep learning algorithms, such as Convolutional Neural Networks (CNNs) in many near-sensor embedded systems, opens new challenges in terms of energy efficiency and hardware performance. An emerging solution to address these challenges is to use tailored heterogeneous hardware accelerators combining processing elements of different architectural natures such as Central Processing Unit (CPU), Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), or Application Specific Integrated Circuit (ASIC). To progress towards heterogeneity, a great asset would be an automated design space exploration tool that chooses, for each accelerated partition of a CNN, the most appropriate architecture considering available resources. To feed such a design space exploration process, models are required that provide very fast yet precise evaluations of alternative architectures or alternative forms of CNNs. Quick configuration estimation could be achieved with few parameters from representative input sequences. This article studies a solution called flydeling (as a contraction of fly weight mo deling ) for obtaining these models by inspiring from the black-box System Identification (SI) domain. We refer to models derived using the proposed approach as fly weight mo dels ( flydels ). A methodology is proposed to generate these flydels , using CNN properties as predictor features together with SI techniques with a stochastic excitation input at a feature map dimensions level. For an embedded CPU-FPGA-GPU heterogeneous platform, it is demonstrated that it is possible to learn these Key Performance Indicators (KPIs) flydels at an early design stage and from high-level application features. For latency, energy, and resource utilization, flydels obtain estimation errors varying between 5% and 10% with less model parameters compared to state-of-the-art solutions and are built automatically from platform measurements.

IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling

Despite the great success of high-level synthesis (HLS) tools, we observe several unresolved challenges: 1) the high-level abstraction of HLS programming styles sometimes conceals optimization opportunities; 2) the actual quality of resulting RTL designs is hard to predict; and 3) existing HLS tools do not provide flexible tradeoff (Pareto) solutions among different objectives and constraints. To this end, we propose an end-to-end framework, namely, IronMan-Pro. The primary goal is to enable a flexible and automated design space exploration (DSE), to provide either optimized solutions under user-specified constraints or Pareto tradeoffs among different objectives (such as resource types, area, and latency). IronMan-Pro consists of three components: 1) GPP, a highly accurate graph-neural-network-based performance and resource predictor; 2) RLMD, a reinforcement-learning-based multiobjective design exploration engine for optimal resource allocation strategies, aiming to provide Pareto solutions among different objectives; and 3) CT, a code transformer to assist RLMD and GPP, which extracts the data flow graphs from original HLS C/C++ and automatically generates synthesizable code with optimized HLS directives. Experimental results show that, 1) GPP achieves high prediction accuracy, reducing the prediction errors of HLS tools by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10.9\times $ </tex-math></inline-formula> in resource utilization and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.7\times $ </tex-math></inline-formula> in critical path (CP) timing; 2) compared with meta-heuristic-based techniques, IronMan-Pro generates superior solutions improving resource utilization by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16.0\% \sim 29.5\%$ </tex-math></inline-formula> and CP timing by 7.6%–16.5%; and 3) under user-specified constraints, IronMan-Pro can find satisfying solutions over 96% of the cases, more than twice as many as that of meta-heuristic-based techniques and with a speedup of up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$400\times $ </tex-math></inline-formula> . This work demonstrates the great potential of applying machine learning algorithms in the electronic design automation domain, especially for the hard-to-solve problems, such as timing estimation and optimization. IronMan-Pro is available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/lydiawunan/IronMan</uri> .

A specification language for automated design space exploration of production systems

Integrating simulation in the design process of production systems allows the predicted performance of design alternatives to be compared. However, many iterations of specifying the design, constructing the simulation model, performing simulation experiments, and evaluating the simulation results for each (re)design are required. The process of specifying, modelling, simulating, and evaluating a design can be automated using a framework for automated design space exploration of production systems. This paper presents a formal specification language for the design space of a production system topology. Using the specification of the design space, feasible designs can be generated. The language supports the specification of component types, component instances, and constraints such as how many instances of a type are allowed and how components are allowed to be connected. The specification language is validated through an adaptation of an industrial case study.

Response surface methodology for design of gas turbine combustor

• Automated design space exploration with CFD quantifies combustor performance. • SST - kω turbulence model with partially premixed FGM combustion model used. • Removing blow-off design points improves response surface prediction accuracy by 57.2% • Pareto fronts from multi objective optimization used for trade-off decisions. • Six sigma DOE analysis quantifies uncertainty in combustor performance. Gas turbine combustor design is a complex multi-objective problem. In the present study, parametric design space study and optimization of a gas turbine combustor using computational fluid dynamics (CFD) simulations is presented. Baseline case validation, automated workflow setup for geometry modification, meshing, boundary condition specification, CFD solution and output parameter calculations are discussed. Response surface methodology is used to study combustor performance based on combustion efficiency, pattern factor, total pressure drop, Carbon monoxide (CO) and Nitrogen oxides (NOx) with variations in three design variables: swirl number, secondary hole diameter and dilution hole diameter. We use central composite design for design of experiments (DOE) and genetic aggregation for response surface generation. Design space refinement is carried out to identify the blow-off region and limit the search space for optimal designs to swirl number greater than 0.9. Exclusion of blow-off design points while generating the response surface resulted not only in 57.2% average reduction of root mean square error in the response surface predictions but also smoother trends away from the blow-off region. A candidate optimal design point with swirl number = 1.0, secondary hole diameter = 12.24 mm and dilution hole diameter = 15.26 mm is chosen using multi objective genetic algorithm on the response surface. Finally, uncertainty quantification with six sigma DOE analysis quantifies the confidence intervals for performance parameters based on the variations in geometric design variables. This preliminary design methodology can be used to improve existing combustors and guide the design of novel combustor concepts.

Automatic RTL Generation Tool of FPGAs for DNNs

With the increasing use of multi-purpose artificial intelligence of things (AIOT) devices, embedded field-programmable gate arrays (FPGA) represent excellent platforms for deep neural network (DNN) acceleration on edge devices. FPGAs possess the advantages of low latency and high energy efficiency, but the scarcity of FPGA development resources challenges the deployment of DNN-based edge devices. Register-transfer level programming, hardware verification, and precise resource allocation are needed to build a high-performance FPGA accelerator for DNNs. These tasks present a challenge and are time consuming for even experienced hardware developers. Therefore, we propose an automated, collaborative design process employing an automatic design space exploration tool; an automatic DNN engine enables the tool to reshape and parse a DNN model from software to hardware. We also introduce a long short-term memory (LSTM)-based model to predict performance and generate a DNN model that suits the developer requirements automatically. We demonstrate our design scheme with three FPGAs: a zcu104, a zcu102, and a Cyclone V SoC (system on chip). The results show that our hardware-based edge accelerator exhibits superior throughput compared with the most advanced edge graphics processing unit.

The TaPaSCo Open-Source Toolflow

The integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.

Automated Design Space Exploration for Optimized Deployment of DNN on Arm Cortex-A CPUs

The spread of deep learning on embedded devices has prompted the development of numerous methods to optimise the deployment of deep neural networks (DNN). Works have mainly focused on: i) efficient DNN architectures, ii) network optimisation techniques such as pruning and quantisation, iii) optimised algorithms to speed up the execution of the most computational intensive layers and, iv) dedicated hardware to accelerate the data flow and computation. However, there is a lack of research on cross-level optimisation as the space of approaches becomes too large to test and obtain a globally optimised solution. Thus, leading to suboptimal deployment in terms of latency, accuracy, and memory. In this work, we first detail and analyse the methods to improve the deployment of DNNs across the different levels of software optimisation. Building on this knowledge, we present an automated exploration framework to ease the deployment of DNNs. The framework relies on a Reinforcement Learning search that, combined with a deep learning inference framework, automatically explores the design space and learns an optimised solution that speeds up the performance and reduces the memory on embedded CPU platforms. Thus, we present a set of results for state-of-the-art DNNs on a range of Arm Cortex-A CPU platforms achieving up to 4x improvement in performance and over 2x reduction in memory with negligible loss in accuracy with respect to the BLAS floating-point implementation.

CNN2Gate: An Implementation of Convolutional Neural Networks Inference on FPGAs with Automated Design Space Exploration

Convolutional Neural Networks (CNNs) have a major impact on our society, because of the numerous services they provide. These services include, but are not limited to image classification, video analysis, and speech recognition. Recently, the number of researches that utilize FPGAs to implement CNNs are increasing rapidly. This is due to the lower power consumption and easy reconfigurability that are offered by these platforms. Because of the research efforts put into topics, such as architecture, synthesis, and optimization, some new challenges are arising for integrating suitable hardware solutions to high-level machine learning software libraries. This paper introduces an integrated framework (CNN2Gate), which supports compilation of a CNN model for an FPGA target. CNN2Gate is capable of parsing CNN models from several popular high-level machine learning libraries, such as Keras, Pytorch, Caffe2, etc. CNN2Gate extracts computation flow of layers, in addition to weights and biases, and applies a “given” fixed-point quantization. Furthermore, it writes this information in the proper format for the FPGA vendor’s OpenCL synthesis tools that are then used to build and run the project on FPGA. CNN2Gate performs design-space exploration and fits the design on different FPGAs with limited logic resources automatically. This paper reports results of automatic synthesis and design-space exploration of AlexNet and VGG-16 on various Intel FPGA platforms.

PaDGAN: Learning to Generate High-Quality Novel Designs

Abstract Deep generative models are proven to be a useful tool for automatic design synthesis and design space exploration. When applied in engineering design, existing generative models face three challenges: (1) generated designs lack diversity and do not cover all areas of the design space, (2) it is difficult to explicitly improve the overall performance or quality of generated designs, and (3) existing models generally do not generate novel designs, outside the domain of the training data. In this article, we simultaneously address these challenges by proposing a new determinantal point process-based loss function for probabilistic modeling of diversity and quality. With this new loss function, we develop a variant of the generative adversarial network, named “performance augmented diverse generative adversarial network” (PaDGAN), which can generate novel high-quality designs with good coverage of the design space. By using three synthetic examples and one real-world airfoil design example, we demonstrate that PaDGAN can generate diverse and high-quality designs. In comparison to a vanilla generative adversarial network, on average, it generates samples with a 28% higher mean quality score with larger diversity and without the mode collapse issue. Unlike typical generative models that usually generate new designs by interpolating within the boundary of training data, we show that PaDGAN expands the design space boundary outside the training data towards high-quality regions. The proposed method is broadly applicable to many tasks including design space exploration, design optimization, and creative solution recommendation.

Accelerating Chip Design With Machine Learning

Recent advancements in machine learning provide an opportunity to transform chip design workflows. We review recent research applying techniques such as deep convolutional neural networks and graph-based neural networks in the areas of automatic design space exploration, power analysis, VLSI physical design, and analog design. We also present a future vision of an AI-assisted automated chip design workflow to aid designer productivity and automate optimization tasks.

Formal Verification and Co-Simulation in the Design of a Synchronous Motor Control Algorithm

Mechatronic systems are a class of cyber-physical systems, whose increasing complexity makes their validation and verification more and more difficult, while their requirements become more challenging. This paper introduces a development method based on model-based design, co-simulation and formal verification. The objective of this paper is to show the applicability of the method in an industrial setting. An application case study comes from the field of precision servo-motors, where formal verification has been used to find acceptable intervals of values for design parameters of the motor controller, which have been further explored using co-simulation to find optimal values. The reported results show that the method has been applied successfully to the case study, augmenting the current model-driven development processes by formal verification of stability, formal identification of acceptable parameter ranges, and automatic design-space exploration.

Enhanced function-means modeling supporting design space exploration

AbstractOne problem in incremental product development is that geometric models are limited in their ability to explore radical alternative design variants. In this publication, a function modeling approach is suggested to increase the amount and variety of explored alternatives, since function models (FM) provide greater model flexibility. An enhanced function-means (EF-M) model capable of representing the constraints of the design space as well as alternative designs is created through a reverse engineering process. This model is then used as a basis for the development of a new product variant. This work describes the EF-M model's capabilities for representing the design space and integrating novel solutions into the existing product structure and explains how these capabilities support the exploration of alternative design variants. First-order analyses are executed, and the EF-M model is used to capture and represent already existing design information for further analyses. Based on these findings, a design space exploration approach is developed. It positions the FM as a connection between legacy and novel designs and, through this, allows for the exploration of more diverse product concepts. This approach is based on three steps – decomposition, design, and embodiment – and builds on the capabilities of EF-M to model alternative solutions for different requirements. While the embodiment step of creating the novel product's geometry is still a topic for future research, the design space exploration concept can be used to enable wider, more methodological, and potentially automated design space exploration.

Towards Multi-objective Optimization of Automatic Design Space Exploration for Computer Architecture through Hyper-heuristic

Towards Multi-objective Optimization of Automatic Design Space Exploration for Computer Architecture through Hyper-heuristic

Towards Multi-objective Optimization of Automatic Design Space Exploration for Computer Architecture through Hyper-heuristic

Multi-objective optimization is an NP-hard problem. ADSE (automatic design space exploration) using heuristics has been proved to be an appropriate method in resolving this problem. This paper presents a hyper-heuristic technique to solve the DSE issue in computer architecture. Two algorithms are proposed. A hyper-heuristic layer has been added to the FADSE (framework for automatic design space exploration) and relevant algorithms have been implemented. The benefits of already existing multi-objective algorithms have been joined in order to strengthen the proposed algorithms. The proposed algorithms, namely RRSNS (round-robin scheduling NSGA-II and SPEA2) and RSNS (random scheduling NSGA-II and SPEA2) have been evaluated for the ADSE problem. The results have been compared with NSGA-II and SPEA2 algorithms. Results show that the proposed methodologies give competitive outcomes in comparison with NSGA-II and SPEA2.