Auto Frequency Calibration Research Articles

A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs

This brief presents a low-power, time-to-voltage converter (TVC)-based auto-frequency calibration (AFC) technology for phase-locked loops (PLLs). Instead of using power-hungry counters and finite-state machine (FSM), the proposed AFC uses TVC and comparator circuits to get the frequency information. Relying on a simple digital operable divide-by-3 (O-Div3) circuit, sampling procedure of TVCs is easy to be realized, which avoids the accumulation of multiple reference periods. Meanwhile, reference frequency is reused, that reduces the cost of extra clock. Beyond that, a binary-like search algorithm is proposed without frequency error. The 4.7-6.8-GHz PLL is implemented in 65-nm CMOS process. The total AFC setting time is less than 750 ns under 20-MHz reference, and consumes below 0.1 mW. Simultaneously, the adopted PLL achieves −116.2-dBc/Hz@1MHz phase noise when generating 4.89-GHz output.

A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

High-Efficiency Class-C <inline-formula> <tex-math notation="LaTeX">$LC$ </tex-math> </inline-formula>-VCO With AFC-Based Phase Noise Compensation

A 4.1–5-GHz voltage-controlled oscillator (VCO) with phase noise insensitive to equivalent resistance ${R} _{\mathrm {p}}$ is presented in this letter. A self-adjusted current resource (SACR) is implemented to alleviate the phase noise deterioration, while the control logic of SACR is compatible with autofrequency calibration resulting in no additional hardware overhead and power. Based on the equivalent internal resistance of the resonant cavity increases with oscillation frequency, the SACR can improve the phase noise and power efficiency. Fabricated in a 180-nm 1P9M CMOS technology, the SACR is employed inside a 4-bit switching capacitance VCO resulting in a tuning range of 4.1–5 GHz and the corresponding phase noise between −124.67 and −128.04 dBc/Hz at a 1-MHz offset. The phase noise is improved by 2.09 dB at 4.1 GHz with SACR.

A modified closed-loop auto frequency calibration technique for a 1.571-GHz integer-N PLL

ABSTRACTIn this paper, a modified closed-loop auto frequency calibration technique (MCL-AFC) is adopted in an integer-N phase-locked loop (PLL) for GPS-L1 application. The ignorance of circuit initial conditions setting in the closed-loop AFC may cause the start-up trap and long frequency calibration time. To solve these problems, the MCL-AFC technique is introduced. The process of MCL-AFC is listed below: first, initialisation process is only used for start-up of PLL; second, closed-loop voltage comparison process and open-loop switching process will take place alternately until optimum frequency control words are obtained. Tuning voltage searching range is reduced by half during the voltage comparison process since VCO’s tuning voltage is set to half of supply voltage through switching process. The MCL-AFC circuit is implemented in a 1-poly 6-metal 180 nm CMOS process and its chip area is 0.0167 mm2. The measured locked output frequency of the PLL is 1.571 GHz and the out-band phase noise is −131.9dBc/Hz at 1 MHz. The calibration time of PLL with MCL-AFC circuit is reduced to only 5µs while whole locking time is about 10.2µs.

2.7–4.0 GHz PLL with dual-mode auto frequency calibration for navigation system on chip

A 2.7–4.0 GHz dual-mode auto frequency calibration (AFC) fast locking PLL was designed for navigation system on chip (SoC). The SoC was composed of one radio frequency (RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator (VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop (PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor (CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is −90 dBc/Hz@100 kHz frequency offset and −120 dBc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about −142 dBm and −155 dBm, respectively. The area of the proposed PLL is 0.35 mm2 and the total SoC area is about 9.6 mm2.

A 1 V 0.18 μm fully integrated integer-N frequency synthesizer for 2.4 GHz wireless sensor network applications

A 1 V low voltage, low power integer-N frequency synthesizer applied for 2.4 GHz wireless sensor network (WSN) applications is presented. The loop parameters of proposed charge pump phase lock loop frequency synthesizer is calculated and verified on the basis of continuous linear model. The proposed voltage controlled oscillator (VCO) consists of a PMOS cross-coupled transistor pair, a NMOS tail current source and a LC resonator. Common-mode 2nd harmonic filters are employed to improve loaded Q factor and suppress noise. LC resonator is optimized and switched capacitor array is used to lower AM---PM noise conversion. Fabricated in TSMC 0.18 μm CMOS process, the measured phase noise of VCO is ?113.4 dBc/Hz@1 MHz, and ?124.5 dBc/Hz@3.5 MHz while the frequency tuning range covers 4.56---5.32 GHz with 1 V voltage supply. The power dissipation is 2.3 mW and corresponding FOM is about ?185 dBc/Hz. With other blocks of dividers, phase frequency detector, charge pump and auto frequency calibration, the die area of the whole fabricated frequency synthesizer is 1.33 mm2 with pads. With 1 V supply voltage and 9.1 mW power consumption, the measured phase noise of the frequency synthesizer is ?121.9 dBc/Hz@1 MHz and ?134.4 dBc/Hz@3.5 MHz respectively, and the reference spur is ?44.5 dBc. The performance of the designed 1 V integer-N frequency synthesizer is suitable for IEEE 802.15.4/ZigBee based 2.4 GHz WSN applications.

Apparatus and method of auto frequency calibration for transducer

An apparatus for automatically calibrating a transducer are disclosed in the present invention, the apparatus comprising: an oscillator, for generating a system frequency; a micro controller, being coupled to the oscillator, for receiving the system frequency; a counting unit, being installed inside the micro processor, for generating at least a clock signal according to the system frequency; a transformer, whose input terminal is being coupled to the counting unit, for receiving the clock signal and transferring the clock signal to be a plurality of exciting signals, the output terminal feedbacks and couples the exciting signals to the interrupting signal input terminal of the micro controller, wherein the a plurality of exciting signals comprising at least a primary oscillating signal and at least a secondary oscillating signal and the amount of the clock signal equals to that of the primary oscillating signal; and a transducer, whose input terminal is being coupled to the transformer, and the transducer is being excited by the exciting signals to generate an output signal. Thus, the micro controller can be dynamically calibrating the frequency of the exciting signal according to the output signal variation of the transducer, and the best transmitting effect can be achieved without being suffered from the variation of external environment such as the temperature, humidity change.

A 4–6.4 GHz LC PLL With Adaptive Bandwidth Control for a Forwarded Clock Link

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A wide range differentially tuned LC PLL using dual switched capacitor VCOs was designed in a 65 nm standard CMOS process for a forwarded clock link. Bandwidth and stability were maintained across the operating range by using open-loop Auto Frequency Calibration (AFC) tuning techniques and an adaptively biased bit-sliced charge pump. The PLL is capable of supporting spread spectrum clock (SSC) modulation with a low peak VCO gain by limiting its operation to the high gain region of the varactors where the capacitance versus voltage curves exhibit the greatest linearity. The VCOs support a frequency range of 4.0–4.8 GHz and 5.87–6.4 GHz. The 2-UI jitter of the forwarded clock at 6.4 Gb/s is 0.9 ps RMS while the long term acumulated <formula formulatype="inline"> <tex Notation="TeX">$N$</tex></formula>-UI jitter for large <formula formulatype="inline"> <tex Notation="TeX">$N$</tex></formula> is 2.1 ps RMS. </para>