Atomistic Quantum Transport Simulations Research Articles

Revealing the influence of edge states on the electronic properties of PtSe2

The properties and performance of 2D nanostructures are known to be critically affected by localized edge states. Here, platinum diselenide (PtSe2) films, synthesized by thermally assisted conversion, are characterized by a variety of spectroscopic and microscopic methods, including scanning tunneling microscopy and spectroscopy, and scanning transmission electron microscopy. We report the presence of distinct edge states, and use surface Green's function methodology in atomistic modeling of different edge atomic structures, together with other theoretical tools, to investigate their origin. Our results indicate that the edges, inherent and abundant in polycrystalline films, can be semiconducting or semimetallic in nature depending on the edge configuration. Experimental results in conjunction with first-principles calculations demonstrate a mapped band profile of the atomically-sharp step edges of PtSe2, which form lateral heterojunctions possessing large asymmetric band offsets in the conduction and valence bands. We further explore the viability of a single step monomaterial heterojunction based field-effect transistor, through atomistic quantum transport simulations. This reveals the critical role of the edge states in creating a wider energy band for carrier transport in the ON-state and hence enabling a remarkably large ION/IOFF ratio > 1010 and near-ideal subthreshold slope, fulfilling the requirements for low-power applications.

Modulation of ballistic injection velocity in phosphorene nanodevices by bias and confinement effects

Atomistic quantum transport simulations are employed to study the electron injection velocity (vinj) and ballistic performance of phosphorene nanoribbon (PNR) field-effect transistors (FETs). We show that PNR bandstructure is immune to quantum confinement effects, which is seen in a rather constant vinj≈2.1 × 107cm/s down to the PNR width of 1.5 nm. Moreover, we demonstrate that the modulation of vinj by gate bias is available only for PNRs wider than 2.1 nm, with the maximum enhancement being 33%. Finally, it is reported that PNR FETs combine high cut-off frequencies above 526 GHz with acceptable bandgap that ranges from 0.7 eV to 1.6 eV in the examined PNR width range, which proves the plausibility of PNRs as channel material for future ultra-scaled high-speed FETs.

Optimum Contact Configurations for Quasi-One-Dimensional Phosphorene Nanodevices.

We employ atomistic quantum transport simulations based on non-equilibrium Green's function (NEGF) formalism of quasi-one-dimensional (quasi-1D) phosphorene, or phosphorene nanoribbons (PNRs), to explore routes towards minimizing contact resistance (RC) in devices based on such nanostructures. The impact of PNR width scaling from ~5.5 nm down to ~0.5 nm, different hybrid edge-and-top metal contact configurations, and various metal-channel interaction strengths on the transfer length and RC is studied in detail. We demonstrate that optimum metals and top-contact lengths exist and depend on PNR width, which is a consequence of resonant transport and broadening effects. We find that moderately interacting metals and nearly edge contacts are optimum only for wider PNRs and phosphorene, providing a minimum RC of ~280 Ωμm. Surprisingly, ultra-narrow PNRs benefit from weakly interacting metals combined with long top contacts that lead to an added RC of only ~2 Ωμm in the 0.49 nm wide quasi-1D phosphorene nanodevice.

(Digital Presentation) Nanowire Transistors with Bound‐Charge Engineering

Low-dimensional electronic systems such as silicon nanowires exhibit weak screening which is detrimental to the performance and scalability of nanodevices, e.g., tunnel field-effect transistors. By atomistic quantum transport simulations, we show how bound charges can be engineered at interfaces of Si and low-κ oxides to strengthen screening. To avoid compromising gate control, low-κ and high-κ oxides areused in conjunction. In Si nanowire tunnel field-effect transistors, we demonstrate that bound charge engineering increases the on-state current by orders of magnitude, and the combination of oxides yields minimal subthreshold swing. Finally, an analytical model is developed for Si nanowire FET assisted by bound charge engineering. We conclude that the proposed bound-charge engineering paves a way toward improved low-power transistors.

Tunneling leakage in ultrashort-channel MOSFETs—From atomistics to continuum modeling

The channel lengths of transistors are now nearing the nanometer, making these devices increasingly prone to direct source-to-drain tunneling (DSDT), a leakage mechanism commonly considered to set the end of Moore’s law. In MOSFETs, the probability for a charge carrier to undergo DSDT decays exponentially with channel length, source depletion length, and drain depletion length. Bound-charge engineering (BCE) is a recently introduced scheme where the depletion lengths of FETs can be controlled through effective doping by surface bound charges residing on the interface between a semiconductor and an adjacent oxide. In this letter, BCE is applied to reduce DSDT leakage current down to acceptable levels in MOSFETs with channels as short as 2.3nm; the higher the oxide permittivity, the lower the DSDT leakage. This idea is tested on ultrascaled Si nanowire MOSFETs via atomistic quantum transport simulations based on the nonequilibrium Green’s function (NEGF) formalism and the tight-binding model, as well as on physically larger Si nanosheet MOSFETs via continuum NEGF–k·p simulations based on the finite-element method.

Lower Limits of Contact Resistance in Phosphorene Nanodevices with Edge Contacts.

Edge contacts are promising for improving carrier injection and contact resistance in devices based on two-dimensional (2D) materials, among which monolayer black phosphorus (BP), or phosphorene, is especially attractive for device applications. Cutting BP into phosphorene nanoribbons (PNRs) widens the design space for BP devices and enables high-density device integration. However, little is known about contact resistance (RC) in PNRs with edge contacts, although RC is the main performance limiter for 2D material devices. Atomistic quantum transport simulations are employed to explore the impact of attaching metal edge contacts (MECs) on the electronic and transport properties and contact resistance of PNRs. We demonstrate that PNR length downscaling increases RC to 192 Ω µm in 5.2 nm-long PNRs due to strong metallization effects, while width downscaling decreases the RC to 19 Ω µm in 0.5 nm-wide PNRs. These findings illustrate the limitations on PNR downscaling and reveal opportunities in the minimization of RC by device sizing. Moreover, we prove the existence of optimum metals for edge contacts in terms of minimum metallization effects that further decrease RC by ~30%, resulting in lower intrinsic quantum limits to RC of ~90 Ω µm in phosphorene and ~14 Ω µm in ultra-narrow PNRs.

A Surface Potential Model for Field-Effect Transistors With Bound-Charge Engineering

Semiconductor doping is limited by such practical concerns as bandgap narrowing and solid solubility limits of dopants. Bound-charge engineering (BCE) bypasses these limits by doping with surface bound charge located on the interface between a semiconductor and an adjacent low-permittivity oxide; it can be used to reduce depletion lengths of junctions in field-effect transistors (FETs). BCE is established by basic electrostatics and is widely applicable to emerging materials and novel devices. In this work, an analytical surface potential model for gate-all-around BCE-assisted silicon nanowire FETs, with arbitrary and possibly distinct spacer and gate oxides, is derived. This model is based on scaling theory and verified against atomistic quantum transport simulations; it provides an intuitive formalism for developing and modeling devices with BCE.

Metallization-Induced Quantum Limits of Contact Resistance in Graphene Nanoribbons with One-Dimensional Contacts.

Graphene has attracted a lot of interest as a potential replacement for silicon in future integrated circuits due to its remarkable electronic and transport properties. In order to meet technology requirements for an acceptable bandgap, graphene needs to be patterned into graphene nanoribbons (GNRs), while one-dimensional (1D) edge metal contacts (MCs) are needed to allow for the encapsulation and preservation of the transport properties. While the properties of GNRs with ideal contacts have been studied extensively, little is known about the electronic and transport properties of GNRs with 1D edge MCs, including contact resistance (RC), which is one of the key device parameters. In this work, we employ atomistic quantum transport simulations of GNRs with MCs modeled with the wide-band limit (WBL) approach to explore their metallization effects and contact resistance. By studying density of states (DOS), transmission and conductance, we find that metallization decreases transmission and conductance, and either enlarges or diminishes the transport gap depending on GNR dimensions. We calculate the intrinsic quantum limit of width-normalized RC and find that the limit depends on GNR dimensions, decreasing with width downscaling to ~21 Ω∙µm in 0.4 nm-wide GNRs, and increasing with length downscaling up to ~196 Ω∙µm in 5 nm-long GNRs. We demonstrate that 1D edge contacts and size engineering can be used to tune the RC in GNRs to values lower than those of graphene.

Nanowire Transistors with Bound-Charge Engineering.

Low-dimensional electronic systems such as silicon nanowires exhibit weak screening which is detrimental to the performance and scalability of nanodevices, e.g., tunnel field-effect transistors. By atomistic quantum transport simulations, we show how bound charges can be engineered at interfaces of Si and low-κ oxides to strengthen screening. To avoid compromising gate control, low-κ and high-κ oxides are used in conjunction. In Si nanowire tunnel field-effect transistors, we demonstrate that bound charge engineering increases the on-state current by orders of magnitude, and the combination of oxides yields minimal subthreshold swing. We conclude that the proposed bound-charge engineering paves a way toward improved low-power transistors.

A computational study of spin Hall effect device based on 2D materials

Efficient spin-charge conversion is indispensable in spintronic computing and memory technologies for achieving low power. Spin Hall and quantum spin Hall effects have been demonstrated in certain atomically thin two-dimensional (2D) materials. In this work, we develop a multiscale simulation method from atomistic quantum transport simulation to the circuit model for the spin Hall effect (SHE) device based on 2D materials. Numerical implementation to speed up atomistic transport simulations with the non-equilibrium Green's function formalism is described for the crossbar SHE device. The multiscale method can treat atomistic scale features and compute the spintronic device performance metrics of the modeled device. As an example, the effect of edge roughness on the SHE devices based on monolayer 2D materials is investigated. The results illustrate that aggressively scaled monolayer SHE devices can efficiently transduce charge to spin in the presence of edge roughness.

Length-Dependent Electron Transport Properties of Defective Silicene Nanoribbons

Electronic and transport properties of realistic silicene nanoribbons (SiNRs) with edge defects are investigated in detail by using statistical atomistic quantum transport simulations based on the non-equilibrium Green's function (NEGF) formalism. We investigate the influence of SiNR width, length, and edge defect density on several parameters relevant for nanoscale device applications, including transport gap, conductance and intrinsic switching capability, mean free path and localization length. Most importantly, we find that a2 nm-wide defective SiNRs with lengths in the 13 nm to 28 nm range are a promising channel material for field-effect transistors at this scale, additionally avoiding the localization transport regime and achieving a variability of 12% to 20% even in the worst case.

Intrinsic Capabilities for Digital Switching of Silicene Nanoribbons With Edge Defects

Statistical atomistic quantum transport simulations are used to study the prospects of digital switching in silicene nanoribbons (SiNRs) with edge defects. For various nanoribbon widths and defect levels, we study the averaged parameters (such as bandgap and conductance in the ON- and OFF-state) and their defect-induced variability. We report that moderately defective SiNRs exhibit up to 30% larger bandgaps than their ideal counterparts, bringing it to about 0.5 eV, and the ON–OFF conductance ratios in the range from ~103 to ~106. In terms of resilience to edge defects, we demonstrate that SiNRs are less immune to defects than phosphorene nanoribbons, while they are considerably more resistant than graphene nanoribbons.

Performance Potential of 2D Kagome Lattice Interconnects

Kagome lattice materials are layered two-dimensional (2D) materials in which atoms are arranged in a trihexagonal tiling lattice pattern. It has been suggested that the Kagome lattice can possess topologically non-trivial band structures. By performing atomistic quantum transport simulations, we show that the topological edge modes of a Fe3Sn Kagome nanoribbon have excellent carrier transport properties, with a mean free path several orders of magnitude larger than that of the bulk modes. Vertical stacking of intercalated Kagome layers can further boost the conductance per unit width. As a result, the 2D Kagome lattice materials offer low resistivity and promising potential for interconnect applications in the sub-10nm regime.

Electron Mobility in Defective Nanoribbons of Monoelemental 2D Materials

Statistical atomistic quantum transport simulations are employed to study electron mobility in silicene, germanene, phosphorene and graphene nanoribbons with edge defects. We demonstrate that silicene and germanene nanoribbons can provide the mobility of up to ≈100 cm2/Vs in the sub-6 nm width range. However, none of these nanostructures appear promising for future extremely-scaled transistors when bandgap-mobility trade-off in defective nanoribbons is considered.

WSe2 Homojunction Devices: Electrostatically Configurable as Diodes, MOSFETs, and Tunnel FETs for Reconfigurable Computing.

In this paper, electrostatically configurable 2D tungsten diselenide (WSe2 ) electronic devices are demonstrated. Utilizing a novel triple-gate design, a WSe2 device is able to operate as a tunneling field-effect transistor (TFET), a metal-oxide-semiconductor field-effect transistor (MOSFET) as well as a diode, by electrostatically tuning the channel doping to the desired profile. The implementation of scaled gate dielectric and gate electrode spacing enables higher band-to-band tunneling transmission with the best observed subthreshold swing (SS) among all reported homojunction TFETs on 2D materials. Self-consistent full-band atomistic quantum transport simulations quantitatively agree with electrical measurements of both the MOSFET and TFET and suggest that scaling gate oxide below 3 nm is necessary to achieve sub-60 mV dec-1 SS, while further improvement can be obtained by optimizing the spacers. Diode operation is also demonstrated with the best ideality factor of 1.5, owing to the enhanced electrostatic control compared to previous reports. This research sheds light on the potential of utilizing electrostatic doping scheme for low-power electronics and opens a path toward novel designs of field programmable mixed analog/digital circuitry for reconfigurable computing.

Quantum Electron Transport in Ohmic Edge Contacts between Two-Dimensional Materials

The metal-semiconductor contact is a major factor limiting the shrinking of transistor dimension to further increase device performance. In-plane edge contacts have the potential to achieve lower contact resistance due to stronger orbital hybridization compared to conventional top contacts. However, a quantitative understanding of the electron transport properties in the edge contact is still lacking. In this work, we present full-band atomistic quantum transport simulations of the graphene/MoS$_2$ edge contact. By using a Wannier function basis to accurately describe the electronic bands, together with a full self-consistent solution of the electrostatics, we are able to efficiently model device structures on a micron scale, but with atomic level accuracy. We find that the potential barrier created by trapped charges decays fast with distance away from the interface, and is thus thin enough to enable efficient injection of electrons. This results in Ohmic behavior in its I-V characteristics, which agrees with experiments. Our results demonstrate the role played by trapped charges in the formation of a Schottky barrier, and how one can reduce the Schottky barrier height (SBH) by adjusting the relevant parameters of the edge contact system. Our framework can be extended conveniently to incorporate more general nanostructure geometries. For example, a full 3D solution of the electrostatics will also lead to better modeling of the electrical potential. Furthermore, better ab-initio calculations can be conveniently added to our methods to further improve their accuracy.

Superior Performance of 5-nm Gate Length GaN Nanowire nFET for Digital Logic Applications

We investigate the performance of 5-nm gate length GaN nMOS nanowire field effect transistor (GaN-NW-nFET) of various geometrical shapes, around the limits of cross-sectional scalability, using atomistic quantum transport simulations. For square cross-sections, the benchmarking results with the simulated Si-NW-nFET reveal over 30% enhancement in GaN drive current in both low standby power (LP − $I_{ \mathrm{\scriptscriptstyle OFF}}=1$ nA/ $\mu \text{m}$ ) and high performance (HP − $I_{ \mathrm{\scriptscriptstyle OFF}}=100$ nA/ $\mu \text{m}$ ) applications. Further performance enhancement is observed with the use of non-square geometries that are akin to GaN’s wurtzite crystal structure. Particularly, for ${T}_{\text {nw}}=2.4 $ mn, triangular cross-section GaN-NW-nFETs exhibit the smallest subthreshold swing, down to 62 mv/decade, excellent drive current, ${I}_{\text {DSAT}} > 2\times 10^{6}\,\, \mu \text {A}/ \mu \text {m}^{2}$ and superior energy-delay product compared to simulated Si-NW-nFET.

Complementary Black Phosphorus Tunneling Field-Effect Transistors.

Band-to-band tunneling field-effect transistors (TFETs) have emerged as promising candidates for low-power integration circuits beyond conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and have been demonstrated to overcome the thermionic limit, which results intrinsically in sub-threshold swings of at least 60 mV/dec at room temperature. Here, we demonstrate complementary TFETs based on few-layer black phosphorus, in which multiple top gates create electrostatic doping in the source and drain regions. By electrically tuning the doping types and levels in the source and drain regions, the device can be reconfigured to allow for TFET or MOSFET operation and can be tuned to be n-type or p-type. Owing to the proper choice of materials and careful engineering of device structures, record-high current densities have been achieved in 2D TFETs. Full-band atomistic quantum transport simulations of the fabricated devices agree quantitatively with the current-voltage measurements, which gives credibility to the promising simulation results of ultrascaled phosphorene TFETs. Using atomistic simulations, we project substantial improvements in the performance of the fabricated TFETs when channel thicknesses and oxide thicknesses are scaled down.

Impact of edge roughness on the electron transport properties of MoS2 ribbons

Edge roughness is expected to play a major role in narrow ribbons obtained from two-dimensional materials, due to the large length/surface ratio of the disordered edges with respect to the whole system surface. In the case of semiconducting transition metal dichalcogenides, a physical and quantitative understanding of the impact of edge roughness on the transport properties of ribbons with nanometer widths is essential in view of their potential applications in ultrascaled nanoelectronics. By means of atomistic quantum transport simulations, we show that the conductance due to edge states within the bulk gap is strongly suppressed by roughness. The corresponding localization length is found to be in the order of few nanometers. At low carrier energies outside the gap, edge roughness drives the system into the diffusive transport regime. The study of the mean free path, under different conditions of roughness and for different ribbon widths, shows that the conductance is moderately affected for widths above 10 nm and lengths in the order of 100 nm, with a more significant degradation for ultra-narrow ribbons.

Intrinsic Performance of Germanane Schottky Barrier Field-Effect Transistors

Germanane (GeH), a hydrogenated germanium monolayer, is a new family of 2-D semiconductors, exhibiting promising potential for electronic device applications. Here, we investigate GeH Schottky barrier (SB) field-effect transistors (FETs) using atomistic quantum transport simulations. Our simulation results reveal that the ohmic-contact device with zero SB height ( $\Phi _{\text {Bn}}$ ) exhibits ~20% lower ON-current than the metal-oxide-semiconductor (MOS) FET counterpart due to the inherent tunnel barrier at the metal–semiconductor junction. We also compare 14-nm-channel GeH and black phosphorus (BP) SBFETs with a finite SB height of $\Phi _{\text {Bn}} = 0.22$ eV for both devices. Our results show that GeH outperforms BP in the ON-state, but it can suffer from larger leakage current in the OFF-state. We further investigate the effect of barrier height in GeH SBFET by varying $\Phi _{\text {Bn}}$ from 0 eV to a half bandgap (0.78 eV). In general, as barrier height increases, both ON-current and the minimum leakage current are reduced. It is also observed that, with increasing SB height, intrinsic delay increases but the required energy per switching decreases, indicating the trade-off between the device speed and the energy dissipation. Our benchmarking of GeH SBFET against GeH and BP MOSFETs demonstrates that GeH generally outperforms BP in terms of energy-delay product (EDP). By performing careful engineering of SB height along with the device threshold voltage, we show that the minimum EDP of GeH SBFET can be as comparable as that of the MOSFET counterpart, suggesting great potential of GeH SBFETs for future switching device applications.