ATLAS Simulation Research Articles

Search for gluino-gluino bound states with ATLAS

The status of the ATLAS simulations of the search for gluino-gluino bound states in the two-jet channel is reported.

VELOCITY-LEVEL KINEMATICS OF THE ATLAS SPHERICAL ORIENTING DEVICE USING OMNI-WHEELS

Using a novel actuation concept employing omni-directional wheels (or simply omni-wheels), the Atlas simulator motion platform provides unlimited angular displacement about any axis. The Atlas concept completely decouples the orienting and positioning degrees-of-freedom and further decouples each of the positioning degrees-of-freedom. It consists of an omni-wheel driven sphere for orientation that has its geometric centre positioned by an $XYZ$-table. The Jacobian of the orienting device is independent of time and dependent only on the mechanism architecture, meaning that it is always invertible for any configuration provided that the initial design parameters do not result in architecture singularities. An examination of the Atlas Jacobian and its determinant identifies architecture singular design conditions. It is found that these are not design limiting. Discussion highlights the uniqueness of the Atlas concept and its associated kinematic advantages.

Enhancement in performance of poly-crystalline thin film transistors with gate dielectric and work-function

In this article, a double gate poly-Si TFT structure is analyzed to study the variation of channel potential profile and threshold voltage with dielectric constant, metal work-function and other device parameters. Green's Function is used to obtain two-dimensional potential distribution. The potential profiles obtained give insight into the device behavior and an estimation of threshold voltage for the device under consideration. Device simulation is also done using ATLAS simulator and the results obtained are compared with proposed two-dimensional model. The modeled results are found to be in good agreement with simulated data.

Two-dimensional analytical threshold voltage model for DMG Epi-MOSFET

A two-dimensional (2-D) analytical model of a dual material gate (DMG) epitaxial (Epi)-MOSFET for improved, SCEs, hot electron effects, and carrier transport efficiency is presented. Using a two-region polynomial potential distribution and a universal boundary condition, we calculated the 2-D potential and electric field distribution along the channel. An expression for threshold voltage for short-channel DMG Epi-MOSFETs is also derived. The ratio of gate lengths has been varied to show which gate length ratio gives the best performance. The analytical results have been validated by the 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.

Quantum confinements in highly asymmetric sub-micrometer device structures

With the ongoing miniaturization of MOSFET structures into the nanometer domain, experimental results suggest there are physical limits up to which one can reduce the gate lengths. Furthermore, it becomes progressively more difficult to overcome the short channel effects at small gate lengths. This has led the researchers in the industry to look for alternative device technologies. One solution to the problem are the asymmetric device structures. In this work, we have simulated a 50 nm asymmetric MOS device structure using a two-dimensional Monte Carlo Poisson particle-based solver, in which quantum effects have been taken into account via the effective potential scheme. The quantum effects in these small device structures lead to strong quantum confinement of the carriers at the semiconductor/oxide interface, thus affecting the device drive current and the threshold voltage. We also show that the Silvaco Atlas simulations performed on the same device structure using the energy balance model were strongly affected by the choice of the energy relaxation times.

Nondestructive current localization upon high-current nanosecond switching of an avalanche transistor

Very good quantitative agreement was found between the experimental and simulated switching transients of a Si avalanche transistor at extreme currents. Two-dimensional (2-D) simulations were performed using the device simulator ATLAS (Silvaco Inc.). Marked current localization was found, which was of a nondestructive character with nanosecond current pulses due to a very significant reduction in the residual voltage across the transistor at high current densities and specific location of the region of intensive heat generation. The device operates reliably at a sufficiently low repetition rate (of a few kilohertz) despite the very high local temperature (/spl sim/750/spl deg/ K) found near the n/sup +/ collector at the end of the switching transient.

Device simulations of nanocrystalline silicon thin-film transistors

In this paper, we present the results of numerical simulations of inverted-staggered thin-film transistors (TFTs) with nanocrystalline silicon channel, using the semiconductor device simulator ATLAS from Silvaco. We study the influence of the density of the acceptor-like defect states concentration on the transistors’ transconductance. Analysis of the free and the trapped carriers’ concentrations at different gate voltages shows that the value of density of defect states determines the behaviour of nanocrystalline silicon TFTs between amorphous and polycrystalline silicon TFTs.

Optimization of on-chip ESD protection structures for minimal parasitic capacitance

Diodes are key components in on-chip electrostatic discharge (ESD) protection design. As the operating frequency of the microchip being protected against the ESD continues to increase, the parasitic capacitance associated with the diodes in the ESD structure starts to impose problems for RF operation. This paper presents a systematic approach to optimize the diode structure for minimal parasitic capacitance based on the requirements of breakdown voltage and heat dissipation. Device simulator Atlas with mix-mode simulation capability is calibrated against measurement data and used to carry out the optimization. An optimized diode structure with a parasitic capacitance of less than 30 fF at an operating frequency of 10 GHz and ESD charging voltage of 1 kV has been suggested. Furthermore, a case study to implement and optimize the ESD protection structure based on an existing 0.13-μm CMOS technology has been presented and verified.

Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency

We propose a new two-dimensional (2-D) analytical model of a dual material gate MOSFET (DMG-MOSFET) for reduced drain-induced barrier lowering (DIBL) effect, merging two metal gates of different materials, laterally into one. The arrangement is such that the work function of the gate metal near the source is higher than the one near the drain. The model so developed predicts a step-function in the potential along the channel, which ensures screening of the drain potential variation by the gate near the drain. The small difference of voltage due to different gate material keeps a uniform electric field along the channel, which in turn improves the carrier transport efficiency. The ratio of two metal gate lengths can be optimized along with the metal work functions and oxide thickness for reducing the hot electron effect. The model is verified by comparison to the simulated results using a 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.

Optimization of FIBMOS Through 2D Silvaco ATLAS and 2D Monte Carlo Particle-based Device Simulations

Focused Ion Beam MOSFETs (FIBMOS) demonstrate large enhancements in core device performance areas such as output resistance, hot electron reliability and voltage stability upon channel length or drain voltage variation. In this work, we describe an optimization technique for FIBMOS threshold voltage characterization using the 2D Silvaco ATLAS simulator. Both ATLAS and 2D Monte Carlo particle-based simulations were used to show that FIBMOS devices exhibit enhanced current drive capabilities when compared to normal MOSFETs. It was also found that the device performance is very much dependent upon the FIB implant profile. High and narrow doping of the FIB implant leads to high drain current and low hot carrier reliability, whereas low and wide doping gives rise to lower drain current and higher hot carrier reliability.

Simulation of electrons irradiation damages to optimize the performance of IGBT

Electron irradiation (IE) is a technique used to control IGBT switching performances and then produce series of IGBTs with various switching velocities. However, this irradiation introduces undesirable effects on other parameters, such as the forward voltage drop and leakage current. In this paper, we propose a method to optimize the performance of the IGBTs considering the degradation effects. The IE effects are simulated using the two-dimensional device simulator ATLAS. Defect densities defined by their energy levels and capture cross section, and densities are introduced into all the structure layers. The energy levels and capture cross sections are extracted from literature and densities are obtained by an iterative process, where the simulated characteristics are fitted to the experimental ones. This method validity is confirmed by comparison of simulation results with experimental ones performed onto a series of IGBTs irradiated to various doses. Steady states and switching characteristics obtained by both simulation and measurements are in good agreement and variations of forward voltage drop versus turnoff time for various doses are obtained and used for performance optimization purposes.

Computer-Based Sensor and Process Fault Diagnosis in Real Time

Computer-based, on-line fault detection and identification in nuclear power plants (NPP’s) by monitoring the time behavior of measurement signals can be performed in three levels. These are the level of hardware redundant signals, the level of processes where methods of analytical redundancy can be applied and the level of closed systems where a new technique using Petri nets has been derived. Methods of the 1st level have already been applied in NPP’s, while a software module related to the 2nd level was tested on-line on a living plant monitoring a steam generator. A Petri net module (3rd level) has been implemented for leak detection and was tested off-line using plant data. Modules of these three levels have been combined to a system for the earLY sensor and process fault detection and DIAgnosis, called LYDIA, for the monitoring of ~ 250 measurement signals of a NPP. LYDIA has been implemented on a parallel processing system. The testing data are generated by the GRS plant simulator ATLAS. The diagnosis based on the modules’ output will be performed on a hybrid AI-system consisting of an expert system and a neural net.

Reconstruction of an arbitrary cross section from the serial drawings of a stereotaxic brain atlas

A method is described for the reconstruction of arbitrary cross sections from the serial line drawings of a stereotaxic brain atlas. Mathematically, the problem reduces to the intersection of a plane with a line pattern lying in another plane. However, the calculation yields a cloud of points, often confusing and unusable for the surgeon. Because it is impossible to link correctly all the calculated points in all cases [1,2], we propose a method where the number of points is drastically reduced: only regions of interest are depicted, i.e., the area where the electrode point is situated and the neighbouring regions. Instead of points, symbols are displayed, each symbol representing a different region. The efficiency of the method is shown using an atlas simulation of four intersecting spheres in the three dimensional space. Although the procedure is useful for all stereotaxic brain atlasses, a practical example is given where the poor quality of the reconstructed images does not allow good interpretation.