Asynchronous Sigma Delta Research Articles

Time Encoding via Unlimited Sampling: Theory, Algorithms and Hardware Validation

An alternative to conventional uniform sampling is that of time encoding, which converts continuous-time signals into streams of trigger times. This gives rise to Event-Driven Sampling (EDS) models. The data-driven nature of EDS acquisition is advantageous in terms of power consumption and time resolution and is inspired by the information representation in biological nervous systems. If an analog signal is outside a predefined dynamic range, then EDS generates a low density of trigger times, which in turn leads to recovery distortion due to aliasing. In this paper, inspired by the Unlimited Sensing Framework (USF), we propose a new EDS architecture that incorporates a modulo nonlinearity prior to acquisition that we refer to as the modulo EDS or MEDS. In MEDS, the modulo nonlinearity folds high dynamic range inputs into low dynamic range amplitudes, thus avoiding recovery distortion. In particular, we consider the asynchronous sigma-delta modulator (ASDM), previously used for low power analog-to-digital conversion. This novel MEDS based acquisition is enabled by a recent generalization of the modulo nonlinearity called modulo-hysteresis. We design a mathematically guaranteed recovery algorithm for bandlimited inputs based on a sampling rate criterion and provide reconstruction error bounds. We go beyond numerical experiments and also provide a first hardware validation of our approach, thus bridging the gap between theory and practice, while corroborating the conceptual underpinnings of our work.

Investigation of Current Reference Schemes in Model Predictive Control and Asynchronous Sigma–Delta Modulation for Control of Single-Phase Inverter

This paper investigates different current reference generation schemes for the control of single-phase inverter-based distributed generator with model predictive control-based space vector modulation and asynchronous sigma–delta modulation schemes. The current references for the developed controller have been deduced from three different schemes, known as scalar, modified scalar and simplified active and reactive power control. The performance of the developed controllers with considered current reference generation schemes is examined for different real and reactive power feedings from the single-phase generator to the grid.

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m CMOS

A new solution for an ultralow-voltage bulkdriven (BD) asynchronous delta-sigma modulator is described in this paper. While implemented in a standard 0.18-μm CMOS process from the Taiwan Semiconductor Manufacturing Company and supplied with VDD = 0.3 V, the circuit offers a 53.3-dB signal-to-noise and distortion ratio, which corresponds to 8.56-bit resolution. In addition, the total power consumption is 37 nW, the signal bandwidth is 62 Hz, and the resulting power efficiency is 0.79 pJ/conversion. The above-mentioned features have been achieved employing a highly linear transconductor and a hysteretic comparator based on nontailed BD differential pair.

Ultra low power design approach of asynchronous delta sigma modulator

Asynchronous Delta Sigma Modulator (ADSM) is assuming an extremely vital part in the majority of conveying device and information convertor and in this manner requires the exceptional consideration in outlining. The execution of the vast majority of the device having DSM as an essential segment is described by the execution of the DSM hardware. This paper introduces the audit of work performed in planning of Asynchronous Delta Sigma Modulator. Latest trends are about the utilization of ADSM for various applications. Contrasting the execution of various ADSM circuits, an execution paradigm is settled for ADSM plan. The execution criteria basically think about the Low working voltages, low power utilization, high SNDR and better focus recurrence. At that point a strategy is suggested that characterizes the High execution ADSM that influence joined utilization of various methods to like inverse operation and mass driven MOS for ultra low power outline and enhancing the execution of an Asynchronous Delta Sigma Modulator.

A 20-nW 0.25-V Inverter-Based Asynchronous Delta–Sigma Modulator in 130-nm Digital CMOS Process

This paper presents a new inverter-based architecture that implements an asynchronous delta–sigma modulator. Different from the classical architecture, it features an input transconductor that promotes a differential and high input impedance that makes it easier to interface with sensors and other front ends. Furthermore, an inverter-based relaxation oscillator accomplishes the required hysteresis through a charge redistribution process, which exhibits lower time delay than hysteretic comparators, besides saving power from quiescent biasing. The circuit has been implemented in 130-nm CMOS digital process using halo-implanted transistors. In addition, transistors are biased in weak inversion and are implemented using distributed layout to reduce power consumption besides mitigating halo-implants undesired effects. Supplied with 0.25 V, the proposed architecture consumes 20 nW with just −55 dB of third harmonic distortion, making it suitable for wearable biomedical applications where energy consumption, low bandwidth, and moderate resolution are required.

Design and Analysis of an Ultra-Low-Power Second-Order Asynchronous Delta–Sigma Modulator

In this paper, a second-order asynchronous delta–sigma modulator is proposed based on the active-RC integrators. The operational transconductance amplifiers used in the integrators are improved by employing a class-AB structure with bulk-driven input drivers and quasi-floating gate method in subthreshold region. These circuitry approaches provide better linearity, signal-to-noise ratio and speed for the integrators and hence an overall improvement in the performance of the modulator. Mathematical analyses of the second-order modulator confirm a higher center frequency compared to a first-order one. The increased center frequency transfers redundancy distortions to higher frequencies, which results in wider input bandwidth and better linearity. The proposed ASDM designed in TSMC 130 nm CMOS Technology with a center frequency of 1.73 kHz at supply voltage of 250 mV with a signal-to-noise-plus-distortion ratio of 67.3 dB and the power consumption of 30 nW.

The use of asynchronous sigma-delta modulation in analog-signal sampling based on event-timing techniques

The possibility of using asynchronous sigma-delta modulation in primary signal converters for precision event timers is considered. A demodulation method based on the moving averaging of a signal and on using the measurements of zero-crossing instants is investigated. The moving averaging of a signal is shown to minimize the effect of timing errors on the accuracy of recovering the waveform of demodulated signals.

Design and Simulation of Power Efficient Linear MOS Transconductor

Objectives: This paper proposes design of a linear and power efficient transconductance amplifier for Asynchronous Sigma-Delta Modulator (ASDM). Methods/Statistical Analysis: The proposed tranconductor circuit uses two linearization techniques which have been combined for design improvement. A triode transistors configuration with cross coupled transistor pair is used to increase the linearity. Findings: The proposed transconductor is specially designed to act as a filter for ASDM. The topology attains a DC gain (Ao) of 25 dB, a Gain-Bandwidth Product (GBW) of 70 MHz, cut-off frequency of 4 MHz and a power consumption of 72.44 μW when used as an integrator. Application/Improvements: Transconductor is simulated in TSMC 0.18μm technology with an operating voltage 1.8 V. Simulation results shows that the power consumption of circuit is very less, which makes it suitable for low power signal processing applications.

Design of resolution/power controllable Asynchronous Sigma-Delta Modulator

This paper presents the design of a Programmable Asynchronous Modulator (PAM) with field control of resolution and power. A novel variable hysteresis Schmitt Trigger (ST) is used for external programmability. Asynchronous Sigma-Delta Modulator (ASDM) implementation with external control voltages is proposed to supervise the resolution and power. This architecture with reduced circuit complexity considerably improves the earlier realizations by eliminating multiple current sources as well switched capacitor circuits and results in power saving up to 87 %. Proposed PAM design demonstrates an improved SNDR of 115 dB, DR of 96 dB, and power consumption below 280 μW. It illustrates Effective Number of Bits (ENOB) to 18.81 and Figure of Merit (FoM) to 0.15 fJ/conversion step. Modulator is implemented in Cadence UMC Hspice 0.18 μm CMOS analog technology. Off-chip PAM control for resolution/power performance has potential applications in battery operated ultra low power applications like IoT; where ADC is one of the major power consuming components. It offers the promise for an efficient performance with power saving.

Design of a low‐voltage op‐amp‐less ASDM to linearise VCO‐ADC

A very simple asynchronous sigma delta modulator design for linearisation of VCO ADC's is presented. The circuit only consists of a passive feedback filter and a Schmitt Trigger. By proper sizing, the non-linearity error can be reduced to well below 0.12% for input signals that go almost rail-to-rail. The design has been manufactured in the low power version of TSMC 65 nm technology and was measured at a 1 V power supply.

Sample-and-Hold Asynchronous Sigma-Delta Time Encoding Machine

In this brief, a new modulation scheme called sample-and-hold asynchronous sigma-delta modulation (SH-ASDM), the extension of the classical asynchronous sigma-delta scheme (ASDM), is introduced. The SH-ASDM is aimed to provide an instantaneous time encoding instead of the mean value encoding realized in the ASDM. This eliminates the effect of the dynamic range reduction of output pulses lengths, which appears for high-frequency input signals in ASDM. SH-ASDM outperforms the ASDM by about 3 dB in the signal-to-noise ratio quantization characteristics, in respect to the worst case input signal. The new analytic model of ASDM is also proposed, which decomposes this type of time-encoding into a linear filtering, sampling, and nonlinear sample transformation.

Effects of fractional order integration on ASDM signals

Pulse density modulation (PDM) can find applications in consumer electronics, power and switch control systems. PDM signals can be generated by asynchronous sigma delta modulator (ASDM) structures and improvement of ASDM performance provides significant contribution for practical applications. This study numerically investigates effects of fractional order integration (FOI) on the PDM signal, produced by ASDM. We implemented fractional order integratorin ASDM structure and present numerical analysis to discuss effects of fractional order integrator on PDM signals, obtained for bipolar digital signal transmission application. Theoretical analysis indicates that FOI provides finer pulse trains and thus improves representation of original signal. In simulations, we tested FOI for various fractional-order values. Signal to noise ratio and signal to noise and distortion ratio (SINAD) levels of demodulated signals are reported for sinusoidal and audio test signals. Simulation results demonstrate that FOI can improve SNR and SINAD performance of ASDMs.

Simplified Reactive Power Control for Grid-connected Photovoltaic Inverters

Reactive power plays an eminent role for the power system to operate efficiently as well as securely. In order to control the reactive power by the proposed Simplified Reactive Power Control (SRPC) strategy for single-phase grid-tied Photovoltaic (PV) inverters. In this proposed SRPC strategy, the reactive power control is achieve effectively by using the Current-Mode Asynchronous Sigma-Delta Modulation (CASDM). This CASDM is adopted to enhance the current control’s dynamic response, reduce both the current harmonic distortion and electromagnetic interference. In this paper, the proposed PV inverter is to extract the maximum power from the PV panels and to inject the corresponding active power into the utility grid. In the meantime, the output reactive power Qout calculated by the simplified power calculation. With both the SRPC and CASDM, the single-phase PV inverter can achieve the desired RPC with low current harmonic distortion.

A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process

In this paper, we present a single-bit clock-less asynchronous delta–sigma modulator (ADSM) operating at just 0.25 V power supply. Several circuit approaches were employed to enable such low-voltage operation and maintain high performance. One approach involved utilizing bulk-driven transistors in subthreshold region with transconductance-enhancement topology. Another approach was to employ distributed transistor layout structure to mitigate the effect of low output impedance due to halo drain implants employed in today’s digital CMOS process. The ADSM achieved a characteristic center frequency of 630 Hz. It had an effective signal-to-noise-plus-distortion ratio (SNDR) of 58 dB or effective number of bits (ENOB) 9 b and just 28-nW power dissipation. A detailed analytical model capturing the effect of nonidealities of the individual circuit components is also presented for the first time with a close agreement with experimental results.

Theoretical study and demonstration of photonic asynchronous first-order delta-sigma modulator for converting analog input to NRZ binary output

Fil: Costanzo Caso, Pablo Alejandro. Consejo Nacional de Investigaciones Cientificas y Tecnicas. Centro Cientifico Tecnologico La Plata. Centro de Investigaciones Opticas (i); Argentina. Rose-Hulman Institute of Technology. Physics and Optical Engineering Department; Estados Unidos

A low-power time-domain VCO-based ADC in 65 nm CMOS

A low-power, high-FoM (figure of merit), time-domain VCO (voltage controlled oscillator)-based ADC (analog-to-digital converter) in 65 nm CMOS technology is proposed. An asynchronous sigma—delta modulator (ASDM) is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR (exclusive-OR) gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic-distortion-cancellation technique to its transconductance stage, which increases the SNDR (signal to noise and distortion ratio) performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO's V—F (voltage to frequency) conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC's low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.

Asynchronous processing of sparse signals

Unlike synchronous processing, asynchronous processing is more efficient in biomedical and sensing networks applications as it is free from aliasing constraints and quantization error in the amplitude, it allows continuous-time processing and more importantly data is only acquired in significant parts of the signal. We consider signal decomposers based on the asynchronous sigma delta modulator (ASDM), a non-linear feedback system that maps the signal amplitude into the zero-crossings of a binary output signal. The input, the zero-crossings and the ASDM parameters are related by an integral equation making the signal reconstruction difficult to implement. Modifying the model for the ASDM, we obtain a recursive equation that permits to obtain the non-uniform samples from the zero-time crossing values. Latticing the joint time-frequency space into defined frequency bands, and time windows depending on the scale parameter different decompositions are possible. We present two cascade low- and high-frequency decomposers, and a bank-of-filters parallel decomposer. This last decomposer using the modified ASDM behaves like a asynchronous analog to digital converter, and using an interpolator based on Prolate Spheroidal Wave functions allows reconstruction of the original signal. The asynchronous approaches proposed here are well suited for processing signals sparse in time, and for low-power applications.

Simplified Reactive Power Control for Single-Phase Grid-Connected Photovoltaic Inverters

The objective of this paper is to propose a simplified reactive power control (SRPC) strategy for single-phase grid-tied photovoltaic (PV) inverters. With the proposed SRPC strategy, a cost-effective microcontroller can be adopted to achieve an effectively reactive power control. Moreover, the current-mode asynchronous sigma-delta modulation (CASDM) is adopted to enhance the current control's dynamic response and reduce both the current harmonic distortion and electromagnetic interference. In this paper, the operational principle of the proposed SRPC is introduced. Then, the small signal analysis for the PV inverter with the CASDM is presented. Finally, a 1-kVA single-phase PV inverter was built to verify the performance of the proposed control strategy.

Asynchronous sigma–delta modulator with noise shaping

A novel architecture of an asynchronous sigma?delta modulator with noise shaping is introduced. Compared with the conventional solution, the proposed modulator achieves first-order noise shaping without an additional loop filter. With the same sampling frequency, the improvement of the SNDR of the asynchronous sigma?delta modulator can be over 20 dB.

Asynchronous Representation and Processing of Nonstationary Signals : A Time-Frequency Framework

Nonstationarity relates to the variation over time of the statistics of a signal. Therefore, signals from practical applications that are realizations of nonstationary processes are difficult to represent and to process. In this article, we provide a comprehensive discussion of the asynchronous representation and processing of nonstationary signals using a time-frequency framework. Power consumption and type of processing imposed by the size of the devices in many applications motivate the use of asynchronous, rather than conventional synchronous, approaches. This leads to the consideration of nonuniform, signal-dependent level-crossing (LC) and asynchronous sigma delta modulator (ASDM)-based sampling. Reconstruction from a nonuniform sampled signal is made possible by connecting the sinc and the prolate spheroidal wave (PSW) functions?a more appropriate basis. Two decomposition procedures are considered. One is based on the ASDM that generalizes the Haar wavelet representation and is used for representing analog nonstationary signals. The second decomposer is for representing discrete nonstationary signals. It is based on a linear-chirp-based transform that provides local time-frequency parametric representations based on linear chirps as intrinsic mode functions (IMFs). Important applications of these procedures are the compression and processing of biomedical signals, as it will be illustrated in this article.