Asynchronous Methodology Research Articles

The Optimization of Hybrid Technology in Synchronous and Asynchronous Speaking Class

In an era characterized by dynamic shifts in the field of education, the pursuit of effective teaching remains a prominent objective. This study investigates a novel methodology that integrates hybrid synchronous and asynchronous methods to enhance students' English language speaking skills in the context of English language instruction. This study commences by underscoring the significance of possessing proficient English-speaking skills. Dynamic learning encompasses a combination of real-time interactions and exercises that can be completed at different times. The objective of this study is to elucidate the perspectives of educators towards the integration of hybrid synchronous and asynchronous methodologies in the instruction of English language skills, specifically in the context of speaking classes. Educators in high school or vocational settings ought to use a blended approach to English language instruction, specifically in the context of speaking courses. The research employed a descriptive case study approach. The study incorporated participants who were engaged in semi-structured interviews that encompassed questionnaires administered with high rates of close-ended responses. The findings of the study indicate that there is a significant impact of social and psychological elements on teachers' proficiency in online communication. The ramifications of these findings are of great importance for educators in the field of English language instruction. The utilization of hybrid synchronous and asynchronous approaches has the potential to enhance students' oral communication abilities within the classroom setting. In summary, the hybrid approach to English instruction, encompassing both ongoing and non-ongoing components, involves the inclusion of proficient-speaking teachers and actively engaged students in speaking-focused sessions.

Health professions’ perspective on emergency remote education

PurposeThe COVID-19 pandemic has created a significant disruption in the educational systems worldwide. Some institutions opted for emergency remote education due to the need to cancel in-person activities. The aims of this paper were to evaluate the use of asynchronous methodology in health sciences education, determine whether asynchronous methodology was sacrificing overall student satisfaction, and investigate whether satisfaction improved as the program develops.Design/methodology/approachInitially, there was phase 1 that corresponded to four weeks of activities. Each professor produced a video lesson, and after each video lesson, a weekly educational activity was made available. Next, phase 2 was implemented using the same methodology, however lasting six weeks. Three questionnaires were developed, and a Likert scale was administered to verify the students’ level of satisfaction. Data were analyzed using frequency distributions, mean values, standard deviation and confidence interval. The normality of the sum data (total of the questionnaires) was tested using the Kolmogorov–Smirnov test.FindingsAlthough the students pointed out that the asynchronous methodology facilitated access to the content and considered this methodology satisfactory, they expressed a reduced level of satisfaction regarding emergency remote education in general when data from the first weeks were compared to those of the previous weeks. It is clear that students became increasingly discouraged and tired over time, which motivated the institution to shift into a combination of synchronous and asynchronous methodology to improve student learning.Originality/valueTeaching in the field of health care encompasses difficult competencies that sometimes are impossible to be learned remotely, so there is a need to examine and evaluate properly the remote education in this area. With careful planning, educational institutions can evaluate their experiences during the pandemic, allowing those involved to highlight strengths and identify weaknesses to better prepare for future needs to improve remote education.

A Comparative Study on Teaching Methodologies Applied in Engineering and Manufacturing Process Subjects during the COVID-19 Pandemic in 2020 and 2021

Specific disciplines in engineering, such as manufacturing processes, require students in their academic stage to pay special attention, given the possible changes that may affect the acquisition of competencies. In an environment of uncertainty, such as a global pandemic, teaching must adapt without losing the effective delivery of content to students. The health and safety measures applied during the first months of the pandemic led to a different type of teaching to that which had customarily been applied, such as synchronous and asynchronous methodologies defined by the university’s governing bodies, where face-to-face and online methodologies coexisted in the same academic year. All of this avoided interrupting the academic year. This paper studies the results achieved in this uncertain environment, extends them and compares them with the following year, where only the face-to-face methodology was applied to the students enrolled in Manufacturing Processes 2 at the Centro Universitario de Mérida within the Bachelor’s Degree in Design Engineering and New Product Development (Grado en Ingeniería en Diseño y Desarrollo de Nuevos Productos -GIDIDP-). An analysis of variance (ANOVA) was applied to the data obtained to locate the significant differences between the samples taken in the first year with online and face-to-face teaching methodologies and those taken in the second year with an exclusively face-to-face methodology. When comparing the results, maintaining face-to-face teaching proved essential, as it contributes towards achieving better marks or maintaining the level. However, online methodologies also help as an additional tool to acquire other knowledge and specific skills in these technical engineering subjects, specifically those dealing with the manufacturing processes addressed in this study.

Comparing Virtual Learning Techniques Upon Technology Acceptance and Student Engagement in Differing Classroom Environment

With divergent educational processes brought forth through the unforeseen circumstances such as a global pandemic, students have become obligated to pursue virtual means towards obtaining their education. Therefore, this study seeks to review the different formats of virtual learning processes and methodologies that are currently made available to students based on student and user perception and technology adoption efforts. Through comparative analysis efforts identifying synchronous, hybrid and asynchronous virtual educational standards across multiple publications and understanding technology acceptance models (TAM) and theories such as perceived usefulness, it is understood that virtual learning efforts which pursue an asynchronous methodology are more comparable in contrast other formats.

Low power aware standard cells using dual rail multi threshold null convention logic methodology

Over the last few decades, low power design has become unease in VLSI design, particularly for movable and high performance systems. Power dissipation is crucial for deep sub – micron technologies. There is a need for efficient leakage diminution techniques to minimize MOS leakage currents. Reduced leakage currents extend the life of all battery operated devices like mobiles, laptops. To reduce the power dissipation in digital VLSI design, we use different types of techniques. Compared to bipolar technology, CMOS technology provides low power dissipation. But, still this topology suffers with high leakage and dynamic power consumption. These hiccups can be overcome by making use of multi-threshold and asynchronous methodologies into the conventional CMOS technology. In this paper, we investigate the performance of various threshold templates and combinational circuits using various low power and asynchronous topologies. Latest topologies like Multi Threshold CMOS (MTNCL) and Multi Threshold Null Convention Logic (MTNCL) are compared with existing CMOS technology in terms of constrains like power dissipation, delay, slew rate and energy performance.

E-Learning Methodologies and Tools

E-learning is among the most important explosion propelled by the internet transformation. This allows users to fruitfully gather knowledge and education both by synchronous and asynchronous methodologies to effectively face the need to rapidly acquire up to date know-how within productive environments. This review paper discusses on e-learning methodologies and tools. The different categories of e-learning that includes informal and blending learning, network and work-based learning. The main focus of e-learning methodologies is on both asynchronous and synchronous methodology. The paper also looked into the three major e-learning tools which are (i) curriculum tools (ii) digital library tools and (iii) knowledge representation tools. The paper resolves that e-learning is a revolutionary way to empower workforce with the skill and knowledge it needs to turn change to an advantage. Consequently, many corporations are discovering that e-learning can be used as a tool for knowledge management. Finally the paper suggests that synchronous tools should be integrated into asynchronous environments to allow for “any-time” learning model. This environment would be primarily asynchronous with background discussion, assignments and assessment taking place and managed through synchronous tools.

Review and comparison of RSFQ asynchronous methodologies

The various design limitations imposed on RSFQ circuits through synchronous clocking schemes, make the use of asynchronous clocking attractive. This paper critically reviews and compares a wide range of asynchronous methodologies that have thus far been proposed in the published literature. Circuits are optimized using a Genetic Algorithm optimizer and are then compared in terms of yield, critical margins and latency. A full-adder is also designed and simulated for each methodology to obtain information regarding implementation above the primitive cell level.

A new asynchronous methodology for modeling of physical systems: breaking the curse of courant condition

Computer simulation of many important complex physical systems has reached a plateau because most conventional techniques are ill equipped to deal with the multi-scale nature of such systems. The traditional technique to simulate physical systems modeled by partial differential equations consists of breaking the simulation domain into a spatial grid and then advancing the state of the system synchronously at regular discrete time intervals. This so-called time-driven (or time-stepped) simulation (TDS) has inherent inefficiencies such as the time step restriction imposed by a global CFL (Courant–Friedrichs–Levy) condition. There is ongoing research on introducing local time refinement (local versus global CFL) within the time-stepped methodology. Here, we propose an entirely different (asynchronous) simulation methodology which uses the spatial grid but the time advance is based on a discrete event-driven (as opposed to time-driven) approach. This new technique immediately offers several major advantages over TDS. First, it allows each part of the simulation, that is the individual cells in case of fluid simulations and individual particles within a cell in case of particle simulations, to evolve based on their own physically determined time scales. Second, unlike in the TDS where the system is updated faithfully in time based on a pre-selected user specified time step, here the role of time step is replaced by a threshold for local state change. In our technique, individual parts of the global simulation state are updated on a “need-to-be-done-only” basis. Individual parts of the simulation domain set their own time scales for change, which may vary in space as well as during the run. In a particle-in-cell (PIC) simulation, DES enables a self-adjusting temporal mesh for each simulation entity down to assigning an individual time step to each particle. In this paper, we illustrate this new technique via the example of a spacecraft charging in a neutral plasma due to injection of a charged beam particle from its surface and compare its performance with the traditional techniques. We find that even in one-dimension, the new DES technology can be more than 300 times faster than the traditional TDS. Aside from sheer performance advantages, the real power of this technique is in its inherent ability to adapt to the spatial inhomogeneity of the problem. This enables building intelligent algorithms where interaction of simulation entities (e.g., cells, particles) follow elementary rules set by the underlying physics laws. Finally, our extensions of this technique to other problems such as the solution of diffusion equation and electromagnetic codes are briefly discussed.

Pivotpoint: clockless crossbar switch for high-performance embedded systems

PivotPoint is a blended synchronous-asynchronous system on chip (SoC). That is, designers employed synchronous and asynchronous methodologies in the design, using whichever was most advantageous for a given region of the circuit. A generally available commercial product, PivotPoint primarily contains high-performance asynchronous logic. Although the technology's promise motivated the design effort, many architecture and methodology innovations occurred along the way in creating a commercially viable clockless IC. Synchronous systems dedicate a significant percentage of the clock period to margin during which there is no useful logical computation. Design margin can be the largest; it is the difference between the worst-case paths in the clock domain, which define the clock period, and the average-case paths. Shrinking this difference requires considerable engineering and/or methodology work.

Design of asynchronous circuits using synchronous CAD tools

Poor CAD support hinders wide acceptance of asynchronous methodologies, and asynchronous design tools are far behind synchronous commercial tools. A new design flow, NCL/spl I.bar/X, based entirely on commercial CAD tools, targets a subclass of asynchronous circuits called null convention logic. NCL/spl I.bar/X shows significant area improvement over other flows for this subclass.

Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor

We describe the design and implementation of an asynchronous discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) processor core compliant with the CCITT recommendation H.261. First, a micropipelined implementation with level-sensitive latches is shown. This is improved by replacing the level-sensitive latches with dual-edge triggered flip-flops to save power and using completion-detection adders in the critical stage of the pipeline to exploit the data-dependent processing delay. Gate-level simulation of extracted layouts indicates that the performance of asynchronous implementations is comparable with that of a synchronous implementation based on an identical architecture. This is because part of the penalty introduced by handshaking circuitry in an asynchronous pipeline can be recovered by exploiting data-dependent processing delays with completion-detection circuitry. In pipelines with significant arithmetic processing such as the DCT/IDCT processor, this is easily accomplished. Our results are encouraging because asynchronous designs do not employ global clocking. In the near future when clock generation, clock distribution, and the power consumed in the clock circuitry become limiting factors in the design of large synchronous application specific integrated circuits (ASICs), asynchronous implementation methodology could be pursued as a real alternative.

High speed externally asynchronous/internally clocked systems

Externally asynchronous/internally clocked (EAIC) systems provide a means of reliable controller design and operation, and incorporate many advantages of both synchronous and fully asynchronous methodologies. The basic memory module of an internally-clocked system is the DFLOP the outputs of which are fully protected from metastability-generated anomalies. As a result, the only input constraint on an internally clocked system is a minimum pulse width corresponding to the frequency of the internal clock. In an internally clocked system, a clock event is not generated until all DFLOPs have resolved into alogically defined state. Because the period of the internal clock depends only on propagation delay through the components of the system, the clock always operates at a maximum possible frequency. Several internally clocked systems, involving both static and dynamic logic, are analyzed by using PSPICE simulations and the results of some real time tests are reported for comparison purposes. The operation characteristics of the DFLOP are analyzed at the component level, and system level comparisons are made with previous work. With submicron CMOS designs using dynamic logic, the internal frequencies of EAIC systems are predicted to exceed 300 MHz with throughputs of less than four ns.

‘Blade Runner’: A real-time speech recognizer

A real-time prototype speech recognizer has been implemented on a 66-processor distributed-memory parallel computer. Simple phrases are recognized in approximately 4 to 10 seconds. Scalability, performance and flexibility are the three main aims of this implementation, the ultimate goal being to construct a large vocabulary speech recognizer which responds quickly. A set of three techniques is investigated in this implementation: asynchronous methodology to minimize synchronization overheads, distributed control to avoid a central communications bottleneck, and dynamic load balancing to provide a flexible response to an unpredictable computational load. The effect on memory, processor time allocation and communications is observed in real-time using hardware monitoring aids.