Synthesis Of Asynchronous Circuits Research Articles

High-Level Asynchronous Concepts at the Interface Between Analog and Digital Worlds

Asynchronous circuits are becoming increasingly important in system design for Internet of Things, where they orchestrate the interface between big synchronous computation components and the analog environment, which is inherently asynchronous and has high uncertainty with respect to power supply, temperature, and long-term aging effects. However, wide adoption of asynchronous circuits by industrial users is hindered by a steep learning curve for asynchronous control models, such as signal transition graphs (STGs), that are developed by the academic community for specification, verification, and synthesis of asynchronous circuits. In this paper, we introduce a novel high-level description language for asynchronous circuits, which is based on behavioral concepts —high-level descriptions of asynchronous circuit requirements, that can be shared, reused, and extended by users, and can be automatically translated to STGs for further processing by conventional asynchronous and synchronous electronic design automation tools, such as Petrify and Mpsat. Our aim is to simplify the process of capturing system requirements in the form of a formal specification, and to promote behavioral concepts as a means for design reuse. The proposed design flow is fully automated in open-source toolsuite Workcraft, and is applied to the development of an asynchronous power regulator.

A New Approach and Tool in Verifying Asynchronous Circuits

Research in asynchronous circuit approach has been carried out recently when asynchronous circuits are presented more widely in electronic systems. As they are more important in human life, their correctness should be considered carefully. Although there are some EDA tools for design and synthesis of asynchronous circuits, they are lack of methods for verifying the correctness of the produced circuits. In this work, we are about to propose a verification method and apply it in making a new version of the PAiD tool that can enable engineers to design, synthesize and verify asynchronous circuits. Experiments in verifying circuits have been also provided in this work.

Low power asynchronous circuit back-end design flow

This paper introduces a framework for the synthesis of low leakage power asynchronous circuits while maintaining performance requirements. In the proposed framework, a high-level description of the system is received and then the corresponding specification will be decomposed into smaller circuits which is possible to be directly mapped into predefined circuit templates. The proposed flow has the advantage of exploiting a new performance metric and presents an efficient methodology for static estimation of average performance of asynchronous circuits with choices at the template level. The leakage reduction is done via simultaneous supply voltage selection, multiple threshold voltage assignment and template sizing. The power reduction techniques are properly encoded in a quantum genetic algorithm and evaluated simultaneously. Experimental results are given for a number of 90nm related benchmark circuits and show that this method reduces the total power by close to an order of magnitude, with no or negligible performance penalty.

Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings

Synthesis of asynchronous circuits from signal transition graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. In this paper, a fully automatic technique for resolving such conflicts by means of insertion of new signals and concurrency reduction is proposed. It is based on conflict cores, i.e., sets of transitions causing encoding conflicts, which are represented at the level of finite and complete unfolding prefixes, and a SAT solver is used to find where in the STG the transitions of new signals should be inserted and to check the validity of concurrency reductions. The experimental results show significant improvements over the state space based approach in terms of runtime and memory consumption, as well as some improvements in the quality of the resulting circuits.

Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend

The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of an HDL-description into a corresponding circuit. This paper presents a method for behavioral synthesis of asynchronous circuits which builds on top of syntax directed translation, and which allows the designer to perform automatic design space exploration guided by area or speed constraints. This paper presents an asynchronous implementation template consisting of a data-path and a control unit and its implementation using the asynchronous hardware description language Balsa. This ldquoconventionalrdquo template architecture allows us to adapt traditional synchronous synthesis techniques for resource sharing, scheduling, binding, etc., to the domain of asynchronous circuits. A prototype tool has been implemented on top of the Balsa framework, and the method is illustrated through the implementation of a set of example circuits. The main contributions of this paper are the fundamental idea, the template architecture and its implementation using asynchronous handshake components, and the implementation of a prototype tool.

High performance asynchronous design flow using a novel static performance analysis method

Asynchronous logic is an important topic due to its interesting features of high performance, low noise and robustness to parameters variations. However, its performance evaluation and optimization are relatively challenging processes due to the dependencies between concurrent events. This paper introduces a framework mainly in the context of performance driven synthesis of asynchronous circuits including systems with choice using buffer insertion technique. In the proposed framework, a high-level description of the system is received in Verilog format powered by some special macros, and then the corresponding specification will be decomposed into smaller circuits which is possible to be directly mapped into predefined circuit templates. The proposed flow has the advantage of exploiting a new performance metric and presents an efficient methodology for static estimation of average performance of asynchronous circuits with choices at the template level. The selected performance model is a probabilistic timed Petri-Net that includes probabilistic choice places to capture the conditional behavior of the system. Since there are no any data handling during the proposed static analyzing leads to very fast performance estimation with enough precise results. The buffer insertion technique is properly encoded in a quantum genetic algorithm and then is exploited after decomposition step during the synthesis flow. This algorithm addresses the problem of identifying the number and location of inserted buffers needed in an asynchronous circuit with choice to satisfy a given average case performance constraint, thereby implicitly minimizes the area for a given average case performance. Experimental results on a set of real systems indicate that our proposed technique can achieve a 34% performance enhancement in average by forcing a 19% area penalty.

Synthesis of Timed Circuits Based on Decomposition

This paper presents a decomposition-based method for timed circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the timed signal transition graph (STG) to include only transitions on the output of interest and its possible trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals, which must be reintroduced into the STG to obtain complete state coding. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which full-state-space methods cannot be successfully applied. The proposed method has been implemented as a part of our tool Nii-Utah Timed Asynchronous circuit Synthesis system (nutas), and its first version is available at http://research.nii.ac.jp/ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">~</sub> yoneda.

Visualisation and resolution of encoding conflicts in asynchronous circuit design

Synthesis of asynchronous circuits from signal transition graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. The refinement process is generally done automatically using heuristics. It often produces suboptimal solutions or sometimes fails to solve the problem. Thus manual intervention by the designer may be required. A framework is presented for an interactive refinement process aimed to help the designer. It is based on the visualisation of conflict cores, i.e. sets of transitions causing encoding conflicts, which are represented at the level of finite and complete prefixes of STG unfoldings.

Lazy transition systems and asynchronous circuit synthesis with relative timing assumptions

This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. Lazy transition systems can be effectively used to model the behavior of asynchronous circuits in which relative timing assumptions can be made on the occurrence of events. These assumptions can be derived from the information known a priori about the delay of the environment and the timing characteristics of the gates that will implement the circuit. The paper presents the necessary conditions to generate circuits and a synthesis algorithm that exploits the timing assumptions for optimization. It also proposes a method for back-annotation that derives a set of sufficient timing constraints that guarantee the correctness of the circuit.

Composition of dependency graphs for asynchronous circuit synthesis based on synchronous circuit scheduling

The results of application of the synchronous circuit scheduling to controlled data flow graph (CDFG) on placing a restriction on the number of usable operators in the circuit are used for specifications in the proposed method for dependency graphs for asynchronous circuit synthesis with the shortest possible execution time. First, in this method, operators are assigned to each operation so that the execution order restriction of the operations by co-use of the operators increases less than it would otherwise. In particular, when conditional branching is involved in the specification, such a branching probability is taken into account. Next, from the binding results, dependency graphs are generated that can be mapped directly to the hardware while the execution sequence restriction of each operation and the conformity of the graphs are taken into account. From the experimental results, it is found that the proposed method functions effectively for the specifications of the actual digital filter and for the hypothetical specifications generated randomly. © 2000 Scripta Technica, Electron Comm Jpn Pt 3, 83(12): 70–77, 2000

Composition of dependency graphs for asynchronous circuit synthesis based on synchronous circuit scheduling

The results of application of the synchronous circuit scheduling to controlled data flow graph (CDFG) on placing a restriction on the number of usable operators in the circuit are used for specifications in the proposed method for dependency graphs for asynchronous circuit synthesis with the shortest possible execution time. First, in this method, operators are assigned to each operation so that the execution order restriction of the operations by co-use of the operators increases less than it would otherwise. In particular, when conditional branching is involved in the specification, such a branching probability is taken into account. Next, from the binding results, dependency graphs are generated that can be mapped directly to the hardware while the execution sequence restriction of each operation and the conformity of the graphs are taken into account. From the experimental results, it is found that the proposed method functions effectively for the specifications of the actual digital filter and for the hypothetical specifications generated randomly. © 2000 Scripta Technica, Electron Comm Jpn Pt 3, 83(12): 70–77, 2000

Synthesis of hazard-free asynchronous circuits based on characteristic graph

To synthesize hazard-free asynchronous circuits from Signal Transition Graphs (STGs), we present a new Characteristic Graph (CG) to encapsulate all feasible solutions of the original STG in reduced size, which compares favorably with the state graph approach. Based on CG, we are able to explore the design space, as well as develop a necessary and sufficient condition for hazard-free realization on a predefined general circuit model, which has not yet been reported. The exact optimization for synthesis is shown to be NP hard. A heuristic method is thus proposed which results in efficient solutions while requiring very little CPU time.

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

In this paper, we present methods for synthesizing multilevel asynchronous circuits to be both hazard free and completely testable. Making an asynchronous two-level circuit hazard free usually requires the introduction of either redundant or nonprime cubes or both. This adversely affects the circuit's testability. However, using extra inputs, which is seldom necessary, and a synthesis-for-testability method, we convert the two-level circuit into a multilevel circuit that is completely testable. To avoid the addition of extra inputs as much as possible, we introduce new exact minimization algorithms for hazard-free two-level logic where we first minimize the number of redundant cubes and then minimize the number of nonprime cubes. We target both the stuck-at and robust path delay fault models using similar methods. However, the area overhead for the latter may be slightly higher than for the former.

A region-based theory for state assignment in speed-independent circuits

State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair of different states in a specification has the same binary encoding. A standard way to approach state coding conflicts is to insert new state signals into the original specification in such a way that the original behavior remains intact. This paper proposes a method which improves over existing approaches by coupling generality, optimality, and efficiency. The method is based on the use of a class of "ground objects", called regions, that play the role of a bridge between state-based specifications (transition systems, TS's) and event-based specifications (signal transition graphs, STG's), We need to deal with both types of specification because designers usually prefer a timing diagram-like notation, such as STG, while optimization and cost analysis work better at the state level. A region in a transition system is a set of states that corresponds to a place in an STG (or the underlying Petri net). Regions are tightly connected with a set of properties that are to be preserved across the state encoding process, namely, 1) trace equivalence between the original and the encoded specification, and 2) implementability as a speed-independent circuit. We will build on a theoretical body of work that has shown the significance of regions for such property-preserving transformations, and describe a set of algorithms aimed at efficiently solving the encoding problem. The algorithms have been implemented in a software tool called petrify. Unlike many existing tools, petrify represents the encoded specification as an STG. This significantly improves the readability of the result (compared to a state-based description in which concurrency is represented implicitly by interleaving), and allows the designer to be more closely involved in the synthesis process. The efficiency of the method is demonstrated on a number of "difficult" examples.

Initialization issues in asynchronous circuit synthesis

A design specification is said to be functionally uninitializable if an initializable implementation cannot be obtained. Due to the absence of any initialization sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for uninitializable circuits. We present a novel procedure for synthesizing initializable asynchronous circuits from functionally uninitializable Signal Transition Graphs (STG). After characterizing the necessary conditions for functional uninitializability, we propose a technique that transforms the original STG into an equivalent, functionally initializable STG. We show that the presence of concurrency provides the designer with an extra degree of flexibility when implementing the circuit. It is shown that initializability can be achieved by sacrificing minimal concurrency and without violating the syntactic properties of the STG required for a hazard-free implementation. The synthesis of a trigger module illustrates this procedure.

On the models for asynchronous circuit behaviour with OR causality

Asynchronous circuits behave like concurrent programs implemented in hardware logic. The processes in such circuits are synchronised in accordance with the dynamic logical and causal conditions between switching events. The classical paradigm, easily represented in most process-oriented languages for concurrent systems modelling, is AND causality, which is often associated with a rendez-vous synchronisation. In this paper we investigate a different, less known paradigm, called OR causality. This paradigm is however different from the classical MERGE paradigm, which is based on mutually exclusive events. Petri nets and Change Diagrams provide adequate modelling and circuit synthesis tools for the various OR causality types, yet they do not always bring the specifier to a unique decision about which modelling construct must be used for which type. We present a unified descriptive tool, called Causal Logic Net, which is graphically based on Petri net but has an explicit logic causality annotation for transitions. It is aimed as the least possible generalisation of Petri nets and Change Diagrams. The signal-transition interpretation of this tool is analogous to, but more powerful than, the well-known Signal Transition Graph. A number of examples demonstrate the usefulness of this model in the synthesis of asynchronous control circuits. It is shown that the extension of the basic, unconditional, firing rule with the one that depends upon the marking of the transition preconditions increases the descriptive power of the model to that of the Turing Machine model and allows the modelling of non-commutative state transition behaviour in a purely causal form.

Synthesis of initializable asynchronous circuits

We show that existing synthesis techniques may produce asynchronous circuits that are not initializable by gate level analysis tools even when the design is functionally initializable. Due to the absence of any initialization sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for these circuits. In this paper, we show that proper consideration of initializability during the asynchronous circuit synthesis procedure can guarantee initializable implementations. We show that the assignment of don't cares during the synthesis procedure affects the initializability of the final implementation. We present a novel implicit enumeration procedure that selectively assigns don't cares to obtain an initializable implementation. Initialization sequences are obtained as a by-product of our synthesis procedure.

Removing CSC violations in asynchronous circuits by delay padding

A novel alternative for removing CSC (complete state coding) violations in asynchronous circuit synthesis for STGs (signal transition graphs) is presented. The main feature of the work is to exploit delays in the physical circuit to remove CSC violations. Its main advantages are that it (i) does not need to obey the noninput constraint and (ii) saves area overhead when a CSC violation in the state graph does not actually appear in the physical circuit. The delay constraint for removing each CSC violation is formulated. Then an algorithm is proposed to derive a consistent set of constraints to ensure that all violations are removed. If a consistent set exists, it is shown that those constraints can always be satisfied by padding delays during hazard analysis, and therefore hazard-free circuits without any CSC violation can be derived. Based on this approach, the marked-graph benchmarks, hitherto unsolvable due to the noninput constraint in existing methods, are now resolved.

Asynchronous circuit synthesis with Boolean satisfiability

Asynchronous circuits are widely used in many real time applications such as digital communication and computer systems. The design of complex asynchronous circuits is a difficult and error-prone task. An adequate synthesis method will significantly simplify the design and reduce errors. In this paper, we present a general and efficient partitioning approach to the synthesis of asynchronous circuits from general Signal Transition Graph (STG) specifications. The method partitions a large signal transition graph into smaller and manageable subgraphs which significantly reduces the complexity of asynchronous circuit synthesis. Experimental results of our partitioning approach with large number of practical industrial asynchronous circuit benchmarks are presented. They show that, compared to the existing asynchronous circuit synthesis techniques, this partitioning approach achieves many orders of magnitude of performance improvements in terms of computing time, in addition to the reduced circuit implementation area. This lends itself well to practical asynchronous circuit synthesis from general STG specifications. >

Synthesis of hazard-free asynchronous circuits with bounded wire delays

This paper introduces a new synthesis methodology for asynchronous sequential control circuits from a high level specification, the signal transition graph (STG). The methodology is guaranteed to generate hazard-free circuits with the bounded wire-delay model, if the STG is live and has the complete state coding property. The methodology exploits knowledge of the environmental delays, speed-independence with respect to externally visible signals, and logic synthesis techniques. A proof that STG persistency is neither necessary nor sufficient for hazard-free implementation is given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>