High performance asynchronous design flow using a novel static performance analysis method

Abstract

Asynchronous logic is an important topic due to its interesting features of high performance, low noise and robustness to parameters variations. However, its performance evaluation and optimization are relatively challenging processes due to the dependencies between concurrent events. This paper introduces a framework mainly in the context of performance driven synthesis of asynchronous circuits including systems with choice using buffer insertion technique. In the proposed framework, a high-level description of the system is received in Verilog format powered by some special macros, and then the corresponding specification will be decomposed into smaller circuits which is possible to be directly mapped into predefined circuit templates. The proposed flow has the advantage of exploiting a new performance metric and presents an efficient methodology for static estimation of average performance of asynchronous circuits with choices at the template level. The selected performance model is a probabilistic timed Petri-Net that includes probabilistic choice places to capture the conditional behavior of the system. Since there are no any data handling during the proposed static analyzing leads to very fast performance estimation with enough precise results. The buffer insertion technique is properly encoded in a quantum genetic algorithm and then is exploited after decomposition step during the synthesis flow. This algorithm addresses the problem of identifying the number and location of inserted buffers needed in an asynchronous circuit with choice to satisfy a given average case performance constraint, thereby implicitly minimizes the area for a given average case performance. Experimental results on a set of real systems indicate that our proposed technique can achieve a 34% performance enhancement in average by forcing a 19% area penalty.