Asymmetrical Degradation Research Articles

Dichotic listening performance with cochlear-implant simulations of ear asymmetry is consistent with difficulty ignoring clearer speech.

There are an increasing number of bilateral and single-sided-deafness cochlear-implant (CI) users who hope to achieve improved spatial-hearing abilities through access to sound in both ears. It is, however, unclear how speech is processed when inputs are functionally asymmetrical, which may have an impact on spatial-hearing abilities. Therefore, functionally asymmetrical hearing was controlled and parametrically manipulated using a channel vocoder as a CI simulation. In Experiment 1, normal-hearing (NH) listeners performed a dichotic listening task (i.e., selective attention to one ear, ignoring the other) using asymmetrical signal degradation. Spectral resolution varied independently in each ear (4, 8, 16 channels, and unprocessed control). Performance decreased with decreasing resolution in the target ear and increasing resolution in the interferer ear. In Experiment 2, these results were replicated using a divided attention task (attend to both ears, report one after sentence completion) in both NH and bilateral CI listeners, although overall performance was lower than in Experiment 1. In Experiment 3, frequency-to-place mismatch simulated shallow CI insertion depths (0, 3, 6-mm shifts, and unprocessed control). Performance mostly decreased with increasing shift in the target ear and decreasing shift in the interferer ear; however, performance nonmonotonicities occurred. The worst performance occurred when the shift matched across ears, suggesting that pitch similarity increases difficulty. The results show that it is more difficult to attend an ear that is relatively degraded or distorted, which may set spatial-hearing limitations for CI users when trying to attend to a target in complex auditory scenes.

Analysis of Negative Bias Illumination Stress Induced Effect on LTPS and a-IGZO TFT

The LTPS and IGZO were the two possible options for next generation displays with its own advantages and disadvantages. In terms of reliability, the LTPS TFT offers the superior threshold voltage stability as compare to the IGZO TFT under the gate bias stress. However, the continuing scaling of the LTPS and IGZO limits the electrical performance at higher voltages. LTPS and IGZO TFT still retains the reliability issues at smaller device dimensions. Therefore, the negative bias stress instability in a-IGZO and LTPS TFT having similar device dimension (width × length) has been investigated and compared. The negative bias stress without illumination shows the good thermal stability and no threshold voltage change in the LTPS TFT. However, under illumination (NBIS), the asymmetrical degradation in the LTPS TFT was observed, shows the degradation in off current (IOFF) almost by two order (10−11 A) due to self-heating effects. Whereas, the NBIS on a-IGZO TFT shows the positive shift in the threshold voltage (ΔVth = 2.71 V), due to the double donor state within a-IGZO and gate insulator. It is noticed that, the LTPS and a-IGZO TFT show different photo-generated carrier behavior under NBIS, which may limit the performance for future CMOS device at smaller dimensions.

Direct current field induced asymmetrical DC-resistivity degradation in SrTiO3-based grain boundary layer ceramic

Abstract Degradation of SrTiO3-based grain boundary barrier layer ceramic was studied by applying a direct current voltage of 40 V for 12 days at room temperature. The degradation of the ceramic mainly showed as an asymmetrical resistivity degradation with the degradation of the reverse resistivity being greater than the forward resistivity. By using a scanning microwave impedance microscopy (SMIM), we observed an asymmetry in carrier concentration within the grain boundaries after the aging treatment. It was proposed that the asymmetrical migration of oxygen ions in O-rich region caused the asymmetrical degradation of resistivity. Direct current induced degradation reduces the effectiveness of ceramics capacitors and great efforts should be made to prevent this type of degradation.

Abnormal behavior with hump characteristics in current stressed a-InGaZnO thin film transistors

We investigated the degradation mechanism of a-InGaZnO TFTs under simultaneous gate and drain bias stress. Gate and drain bias of 20V were applied simultaneously to induce current stress, and abnormal turn-around behavior in transfer characteristics with a hump phenomenon were identified. Hump characteristics were interpreted in terms of parasitic current path, and the degradation itself was found to be caused dominantly by the electrical field and to be accelerated with current by Joule heating. The mechanism of asymmetrical degradation after current stress was also investigated. By decomposing the curves into two curves and measuring the relaxation behavior of the stressed TFTs, we also found that abnormal turn-around behavior in the transfer characteristics was related to acceptor-like states.

Impact of repeated uniaxial mechanical strain on flexible a-IGZO thin film transistors with symmetric and asymmetric structures

This letter investigates repeated uniaxial mechanical stress-induced degradation behavior in flexible amorphous In-Ga-Zn-O thin-film transistors (TFTs) of different geometric structures. Two types of via-contact structure TFTs are investigated: symmetrical and UI structure (TFTs with I- and U-shaped asymmetric electrodes). After repeated mechanical stress, I-V curves for the symmetrical structure show a significant negative threshold voltage (VT) shift, due to mechanical stress-induced oxygen vacancy generation. However, degradation in the UI structure TFTs after stress is a negative VT shift along with the parasitic transistor characteristic in the forward-operation mode, with this hump not evident in the reverse-operation mode. This asymmetrical degradation is clarified by the mechanical strain simulation of the UI TFTs.

The effect of device electrode geometry on performance after hot-carrier stress in amorphous In-Ga-Zn-O thin film transistors with different via-contact structures

In this letter, the effects of hot carriers on amorphous In-Ga-Zn-O thin film transistors (TFTs) of different geometric structures were investigated. Three types of via-contact structure TFTs are used in this experiment, defined as source-drain large (SD large), source-drain normal (SD normal), and fork-shaped. After hot-carrier stress, the I-V curves of both SD normal and fork-shaped TFTs with U-shaped drains show a threshold voltage shift along with the parasitic transistor characteristic in the reverse-operation mode. Asymmetrical degradation is exhibited in an ISE-TCAD simulation of the electric field, which shows the distribution of hot electrons injected into the etch-stop layer below the redundant drain electrode.

Asymmetrical degradation behaviors in amorphous InGaZnO thin-film transistors under various gate and drain bias stresses

The asymmetrical degradation behaviors of amorphous indium–gallium–zinc oxide thin-film transistors are studied comprehensively under various gate and drain bias stresses. The transfer curve moves to the negative direction after bias stresses are applied, and different types of asymmetrical degradation are observed depending upon the magnitude of the applied gate and drain bias stresses. After the application of gate-to-source (VGS) and drain-to-source (VDS) bias stresses of (VGS = 16 V, VDS = 16 V) and (VGS = 22 V, VDS = 10 V), the forward mode transfer curve exhibits a more negative shift compared to that of the reverse mode, whereas opposite results are observed under the stress condition of (VGS = 10 V, VDS = 25 V). From the two-dimensional simulation results and the separately extracted subgap density of states in the source and drain sides of the thin film transistors before and after the application of various bias stresses, the local high electric field-induced nonuniform generation rate of the subgap states near the conduction band edge is considered to be the dominant mechanism causing the asymmetrical degradation of the devices under various gate and drain bias stresses. The generation of the subgap states is observed at different locations depending upon the magnitude of the applied gate and drain bias stresses.

Systematic Investigations on Self-Heating-Effect-Induced Degradation Behavior in a-InGaZnO Thin-Film Transistors

This paper investigates degradation behavior induced by the self-heating effect for InGaZnO (IGZO) thin-film transistors (TFTs). Both the surrounding oxide and other thermal insulating materials, as well as the low thermal conductivity of the InGaZnO layer itself, cause the self-heating effect in InGaZnO TFTs. The heated channel layer enhances the threshold voltage shift, and the evolution of threshold voltage shift is found to be dominated by charge-trapping effects. Moreover, a nonuniform distribution of channel carrier concentration leads to an uneven temperature distribution throughout the IGZO active layer, which results in the asymmetrical degradation behavior after the self-heating operation. Further verifications indicate that the degree of the threshold voltage shift is only dependent on stress power, regardless of stress <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vg</i> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vd</i> , and channel length. Further, two-stage dependence of the threshold voltage shift on dynamic stress frequency is found.

Origin of self-heating effect induced asymmetrical degradation behavior in InGaZnO thin-film transistors

This letter investigates asymmetrical degradation behavior induced by the self-heating effect in InGaZnO thin-film transistors. Both the surrounding oxide and other thermal insulating material, as well as the low thermal conductivity of the InGaZnO layer itself, cause the self-heating effect in InGaZnO thin-film transistors. The heated channel layer enhances threshold voltage shift, and the evolution of threshold voltage shift is found to be dominated by charge-trapping effect. Moreover, a non-uniform distribution of channel carrier concentration leads to an uneven temperature distribution through the InGaZnO active layer and results in the asymmetrical degradation behavior after self-heating operation.

The asymmetrical degradation behavior on drain bias stress under illumination for InGaZnO thin film transistors

This paper investigates behavior of drain bias stress and gate-drain bias stress under illumination for InGaZnO thin film transistors as the current-driver operated. Properties exhibit two-stage degradation behavior during drain bias stress. The photo-excited hole non-uniform trapping from illumination induces drain side barrier lowering and causes an apparent hump phenomenon of the subthreshold swing. However, the positive threshold voltage shift without a hump phenomenon after gate-drain bias stress is different degradation behaviors. It is reliant on whether or not an inversion layer exists in the channel. This work also employs capacitance-voltage measurement to further clarify the mechanism of degradation behaviors.

Thermally stimulated currents as a measure of degradation of zinc oxide varistors

ZnO varistor degradation phenomena was studied using thermally stimulated current (TSC) method. It is believed that asymmetrical degradation of V-I characteristics caused by DC biasing is due to charge accumulation on the reverse biased side of ZnO grain barrier. The TSCs' measuring system and cryostat apparatus used in experiment were described. The thermally stimulated currents observed in this study for varistor samples doped with different amounts of Co, due to their recovery from asymmetrical electric stress, could not be controlled by movement of Zn interstitials with activation energy 0.55 v eV, as it is widely believed, for the TSC activation energy determined in this experiment was 0.39 v eV.

Conduction mechanism of non-Ohmic zinc oxide ceramics

The conduction mechanism of non-Ohmic ZnO ceramics is investigated. In order to explain the non-Ohmic property, a new energy-band model composed of a thin intergranular layer with traps sandwiched between Schottky barriers formed opposite each other is proposed. According to the newly proposed energy-band model, the non-Ohmic property of ZnO ceramics is mainly governed by field emission for the reverse-biased Schottky barrier in the voltage region above the threshold voltage in the V-I curve and by thermionic emission in the voltage region below the threshold voltage. The energy-band model and the conduction mechanism discussed in this paper are appropriate for the explanation of experimental results, not only those presented in previous papers, such as the effect of additives, the V-I curve and its temperature dependence, but, additionally, the dielectric properties, the asymmetrical degradation of the V-I curve, and the thermally stimulated current.