This paper proposes a novel design of an 11-transistor SRAM bit-cell with a single-ended structure and memory mini-array with the bit-interleaving architecture support using the gate-diffusion input (GDI) method based on the gate-wrap-around (GWA) CNTFETs technology. The cell core of the suggested design is composed of a robust cross-coupled structure of two asymmetric inverters based on circuit-level methodologies. The proposed bit-cell scheme exhibits significant features such as improved write-ability, read data stability, and reduced leakage/short-circuit power due to the asymmetric write-assist method and inverter gates with stacked transistors, respectively. The simulation analysis has been done based on criteria such as static noise margins (SNMs), power-delay product (PDP), and the electrical quality/yield-based figure of merits (FoMs) in write/hold/read operation cycles. The suggested SRAM bit-cell demonstrates the best results with an average of 9.36 %, 48.53 %, and 22.82 %, respectively, for FoMs against other SRAM bit-cell schemes. The Monte-Carlo simulations in the 16-nm node show better results for the proposed bit-cell in the energy and failure probability per operation cycles than similar designs, with the best performance on average of 27 % and 8 %, respectively.Finally, to investigate the effectiveness of the suggested memory cell in the real application domain, an on-chip scaled power supply memory architecture for storing digital data based on quick response (QR) code using the proposed hardware algorithm is evaluated. Our results certify that the suggested memory array configuration in comprehensive FoMs based on quality and hardware efficiency metrics shows better results than the counterpart memory architecture.
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Sep 1, 2024
Mamatha Narayana + 1
Open Access