Association Process Research Articles

An associative processor array for image processing

This paper describes work carried out on associative processor arrays for image processing. The architecture of a new VLSI associative processor, called GLiTCH, is defined and compared with similar image processing arrays. Simulation results are presented for GLiTCH systems performing a range of image processing tasks.

Self induced coherent light resonators with photorefractive KNbO3crystals

Abstract Associative optical memories have attracted increasing interest as they can offer new, all-optical solutions to various problems, for example in pattern recognition. In such memories, stored informations are retrieved from partial or noisy inputs. An optical laser resonator can act as such an associative processor. Using holograms, different images are associated to each of the modes of the optical cavity. Thus a partial input image can force the resonator to oscillate on the closest stored information. Two wave mixing arrangements in photorefractive crystals, which provide very large amplification factors, can be used to overcome the large losses inherent to these resonators.

High Speed Matrix Preprocessing On Analog Optical Associative Processors

The accuracy of matrix computations performed on analog optical associative processors is limited by noise and spatial wavefront errors. Earlier studies show that the rate of convergence and accuracy of analog optical matrix data processing can be improved by lowering the condition number of the data matrix. In this paper, we describe a new preprocessing technique, the split-step polynomial preconditioning algorithm, that can reduce the condition number of a matrix efficiently. With a few additional steps, this algorithm can be used to calculate the inverse or to estimate the condition number of a matrix. A realization of this preprocessing algorithm on optical associative processors is considered, and its performance and complexity are analyzed. The results of numerical experiments on case studies with ill-conditioned matrices show that this new preprocessing algorithm is a practicable tool for improving the perfor-mance of analog optical processors. Preliminary analyses of the new preconditioning algorithm demonstrate its robustness with regard to the spatial errors and random noise present in most analog optical computing systems.

Nonlinear holographic associative memories

Recent progress in the field of holographic optical associative memories is reviewed. The addition of nonlinear optical feedback to holographic memories using phase conjugation techniques has resulted in a new class of nonlinear holographic associative memories. These systems perform associations between input patterns and stored patterns as in classical holography. Unlike classical holography, however, external nonlinearities are used to make decisions and select between competing alternatives, perform error corrections, and increase storage capacity. Such optical associative processors may have applications in future implementations of optical neural networks. >

A reconfigurable fully parallel associative processor

An associative parallel processing system using novel VLSI associative memory is described. By optimizing the VLSI associative memory architecture, the restrictions that are generally ascribed to classical associative memory systems no longer exist. High performance is achieved without sacrificing memory density due to enhancements in the peripheral circuitry rather than in the storage cell. Using the chip as a basic building block, a dynamically reconfigurable associative processor is proposed. A shifter interconnection network provides the interchip communication required to emulate different networks with a constant routing time for processor data transfers. It also allows for fast communication with a host computer. Parallel arithmetic algorithms are given, together with the application of the Associative Processor to diverse areas such as computer graphics, image processing, and list processing. Results are summarized to show the power of the proposed associative machine which proves to be a general-purpose parallel processor with a broad range of applications.

Key and recollection vector effects on heteroassociative memory performance

Most associative memory work has concentrated on autoassociative memories (AAMs). These associative processors provide reduced noise and error correction in their output data. We will consider heteroassociative memories (HAMs), which are needed to provide decisions on the class of the input data and inferences for subsequent processing. We derive new equations for the storage capacity and noise performance of HAMs, emphasize how they differ from those derived for AAMs, suggest new performance measures to be used, and show how different recollection vector encodings can improve HAM performance.

Special section on associative processors and memories

Special section on associative processors and memories

Flag-algebra: a new concept for the realisation of fully parallel associative architectures

The paper describes a new concept for the design of parallel-working associative memory and processor architectures, which is able to process arithmetical operations as well as complex search-operations for the sets of data in parallel. The proposed concept is based on a transformation method. It maps a set of word-oriented data into flag-oriented data. Each word of the set is represented each by a flag in a flagvector. The position of a flag in the flagvector is defined by the transformation and corresponds to the value of the transformed word. To obtain parallelism for various operations, the flags of the flagvector will be processed simultaneously. The result of these operations will also be flags. They can be retransformed to word-oriented data. A new algebra called flag-algebra to investigate operations on the flagvector will be introduced. This algebra is the isomorph to the set-theory and Boolean algebra. The most important axioms and laws of calculation in this algebra will be described. They can be seen as a substantial basis for the development of flag-oriented hardware systems. Based on this algebra, the architecture of an associative monoprocessor will be presented to process arithmetical as well as complex search operations in parallel. Furthermore, some languages adequate for this architecture and the performance of the processor will be discussed.

Design of an associative processor array

The architecture of a new associative processor array chip, working name GLiTCH, is described and details are given of the techniques used in its VLSI design. The low-level operating characteristics of the chip are explained. A number of system configurations are explored and finally the use of GLiTCH in a vision processing module, currently being designed, is described. >

Optimal number of disc clock tracks for block-oriented rotating associative processors

Block-oriented rotating associative processors provide a highly cost-effective solution to the need for parallel processing of large volumes of data in information storage and retrieval applications. Such processors are implemented by incorporating some processing logic into each read/write head of a fixed-head (head-per-track) disc memory. With non-self-clocked data recording, which offers higher storage densities, the usual data storage format is to assign the fixed capacity dictated by the maximum bit density and the length of the innermost (shortest) track to all tracks, thus making it possible to use a single clock track for the synchronisation of read and write operations. In the paper, we note that with a single clock track about half of the total recording capacity of the disk surface is wasted. This leads to the proposal for dividing the tracks into groups, with one clock track for each group. It is shown that with optimal design, 90–95% of the useful disk capacity can be utilised. This represents a 70–90% improvement over the case of a single clock track and is achieved at virtually no extra cost.

Modeling the process of problem-solving by associative networks capable of improving the performance.

In this paper a model of neural network underlying arithmetic problem-solving is described. Memory models of procedural memory, semantic memory, and working memory, which are necessary to represent the process of the problem-solving, are constructed within a framework of a model of associative processor, HASP, proposed by one of the authors (Hirai 1983). Performance of the model has been simulated on a digital computer. By memorizing primitive knowledge of addition of two digits such as 6 + 8 = 14 in the semantic memory and procedural knowledge for the control of the process of adding in the procedural memory, the model can perform addition of multiple numbers with multiple digits. By making explicit serial associations between consecutive procedural steps, the performance of the model can be improved, because a current procedural step primes the next one. In addition, if a preceding procedural step is a subset of the next one, merging between the two steps occurs. The performance can be improved about 20% by these priming and merging. By memorizing incorrect procedures, the model can generate four kinds of bugs of addition which were observed in children's performance.

Representation of problem—solving processes by a model of associative processor hasp. a case study for the process of addition

AbstractThis paper aims at a constructive description of which neural network model can represent the human problem‐solving process and how the process is related to the various human memories by what context. From such a viewpoint, a neural network model is constructed for the representation of the problem‐solving process. In this paper, a model for the addition process is constructed as the first step, using the associative memory model HASP (human associative processor) proposed by one of the present authors. The model is composed of the following components: the procedure memory, which stores and retrieves the procedures of the addition; semantics memory, which stores the knowledge about the addition such as 2 + 2 = 4; the working memory, which temporarily stores the external and internal information; and the goal memory, which stores the problem‐solving process as a chain of subgoals, and manages the flow of procedures from one higher level in the control hierarchy. In this study, a computer simulation was performed for the addition processes for several numbers with multiple digits, and it is shown that the addition process can be represented. Then the computer simulation is made for the generation of four kinds of bugs in the addition. It is shown that the bug generation can be represented by the model.

An associative string processor architecture for parallel processing applications

An associative string processor architecture for parallel processing applications

Directed graph for adaptive organization and learning of a knowledge base

A directed graph is considered for organization of a knowledge base for neural, associative, model-based, and other advanced processors. Its ability to self-organize itself, delete old information, and add new information and its many interconnections make it most suitable for optical realization and use in advanced neural and adaptive optical processors. An alphanumeric image space example is used as a case study, and an optical processor architecture to achieve this with impressive performance is discussed.

Psychological validity of a model of human associative processor (hasp)

AbstractThis paper discusses the psychological validity of the associative model HASP, which was propsoed by one of the authors. The fan effect and the priming effect are important properties of the retrieval process in human memory. The fan effect is a phenomenon that when the number of items associated with a concept is increased, a longer time is required to select an item from those items. In HASP, one of the multiply matched associative items is selected by the competitive circuit. The fan effect can be ascribed to the delay in the selection due to the increased number of competitions. The priming effect is a phenomenon where the preceding information processing affects the succeeding processing. Depending on the relation between the consecutive information, the effect can be accounted for by the activation of the preceding information left in HASP. It is also shown that the priming effect in the unconscious processing condition, where the cognition of the preceding information is prevented, can also be accounted for. Furthermore, it is shown that the processing in HASP is well matched to the two‐level theory in lexical retrieval, where the semantic selection process for the lexically ambiguous word is composed of the processes of activating all meanings and of selecting the one matched to the context.

Design, selection and implementation of a content-addressable memory for a VLSI CMOS chip architecture

The paper reports an investigation into the design constraints, trade-offs and implementation issues involved in the design of a large content-addressable memory (CAM) for a VLSI CMOS high-speed associative chip architecture: the single chip array processing element SCAPE associative parallel processor. It includes results from a study into determining the general electrical and physical characteristics of a range of CAM cells; details from a case study of the SCAPE chip that predicts the performance of CAMs within a VLSI-based parallel processing computer system, together with the overall impact the CAM design has on the SCAPE chip performance; the selection and implementation engineering of the most cost-effective CAM design for the SCAPE chip.

Representation of Procedural Knowledge by a Model of Human Associative Processor (HASP)

AbstractA human associative processor (HASP) proposed by the author was developed and applied to procedural knowledge. The first step is a simple positive‐feedback model in which the output of a conventional HASP is fed back to its own key input. The chain of a procedure is memorized by taking the positive‐feedback input as the key input of the association, and by associating with the next procedure. A series of computer‐simulation studies showed that the model could express control structures such as wait, jump, do‐while, if‐then, and case control procedures. The second step shows that the simple positive‐feedback model sometimes cannot read the memorized procedure correctly; then an improved model was proposed. In the improved model structure, a converted orthogonal pattern from the positive feedback point and the external input key are used again as the key input. The improved model can read all the memorized procedures correctly; this was confirmed by computer simulation. It was also shown that the pattern completion function associated with the whole procedure from its part, can be represented by noise environmentalization.

Progress on the spin chip associative processor: [formula omitted]. Computer Science Department, University of California, Los Angeles, CA 90024 USA

Progress on the spin chip associative processor: [formula omitted]. Computer Science Department, University of California, Los Angeles, CA 90024 USA

Optical associative processor for general linear transformations

A new technique for the realization of general linear transformations using associative memories is described. An optical architecture for its implementation is also presented. A low-level feature space processor using this architecture is proposed. The processor is capable of recognizing and locating objects of various shapes and uses certain linear transformations in the feature space for distortion invariance.

Model-based knowledge-based optical processors

An efficient 3-D object-centered knowledge base is described. The ability to on-line generate a 2-D image projection or range image for any object/viewer orientation from this knowledge base is addressed. Applications of this knowledge base in associative processors and symbolic correlators are then discussed. Initial test results are presented for a multiple degree of freedom object recognition problem. These include new techniques to achieve object orientation information and two new associative memory matrix formulations.