Aspect Ratio Vias Research Articles

Effect of surface kinetics on the step coverage during chemical vapor deposition

Profile evolution simulations during chemical vapor deposition based on a 2D continuum model reveal that the type of surface kinetics plays an important role in determining step coverage of films deposited in high aspect ratio trenches and vias. Linear surface kinetics, resulting from an adsorption rate limited process, is found to cause difficulty in bringing about conformal step coverage in deep narrow trenches without reducing the growth rate considerably. Under such condition, void-free filling cannot be achieved while maintaining a growth rate acceptable to integrated circuit (IC) manufacturing. The numerical study also suggests that the high tendency of the precursor for chemical equilibrium on a surface, resulting in nonlinear kinetics by a surface reaction limited process, is crucial to achieve a uniform step coverage as typically observed in SiO2 deposition from tetraethylorthosilicate (TEOS).

Ionized titanium deposition into high aspect ratio vias and trenches

The deposition of titanium into high aspect ratio vias and trenches is investigated using ionized physical vapor deposition (I-PVD). Sputtered titanium atoms are ionized by a high density, inductively coupled plasma of argon at 10 and 30 mTorr. The Ti+is then collimated by the plasma sheath and directionally deposited into vias and trenches ∼1 μm in width. The ability of I-PVD to deposit titanium at the bottom of narrow, deep vias and trenches is characterized by cross sectional scanning electron micrographs. The bottom coverage of 3:1 aspect ratio vias increases from 45% to 75% as the argon pressure and plasma density increase. The percentage of titanium flux that is ionized by I-PVD is extracted from analysis of bottom coverage data and falls between 50% and 85%. A method of extracting the effective transverse temperature of Ti+ is also developed. Transverse temperatures increase from 0.13 to 0.18 eV as argon pressure and radio frequency power are increased.

Numerical Simulations of Topographic Evolution for Sputter Deposition into Trenches and Vias

AbstractWe have performed 2D and quasi-3D numerical simulations of physical vapor deposition (PVD) into high aspect ratio trenches and vias used for modem VLSI interconnects. The topographic evolution is modeled using (continuum) level set methods. The level set approach is a powerful computational technique for accurately tracking moving interfaces or boundaries, where the advancing front is embedded as the zero level set (isosurface) of a higher dimensional mathematical function. First, we study the 2D case of long rectangular trenches including 3D out-of-plane target flux. The 3D flux is obtained from molecular dynamics computations for AI(100), and hence our approach represents a hybrid atomistic/continuum model. We obtain good agreement with X-TEM data. Secondly, we report results of axisymmetric 3D simulations of high aspect ratio vias which we then go on to compare with experimental data for Ti/TiN barrier layers. We find that the simulation data (using the cosine angular distribution) overpredict bottom coverage in some cases by approximately 20%-30% for both collimated and uncollimated deposition but in other cases provide a reasonably accurate comparison with experiment.

Homogeneous Tungsten Chemical Vapor Deposition on Silane Pretreated Titanium Nitride

Homogeneous nucleation of tungsten chemical vapor deposition (CVD) films on metallorganic (MO) CVD substrates has been achieved by pretreating the substrate with at a wafer susceptor temperature of . Deposition of approximately a monolayer of silicon from the pretreatment results in continuous, uniform tungsten films less than thick. Tungsten nucleation films grown on MOCVD without a pretreatment were heterogeneous, with tungsten islands not coalescing into a continuous film until the thickness reached . Experimental results are presented along with implications for use of tungsten CVD for vertical interconnects in high aspect ratio vias. ©1999 The Electrochemical Society

Pulse Reverse Copper Electrodeposition in High Aspect Ratio Trenches and Vias

A theoretical model, based on a one‐dimensional approximation, for the filling of high‐aspect ratio trenches and vias with copper by pulse reverse electrodeposition is presented. The dependence of void size on the pulse waveform is demonstrated for submicron features. It is shown that the off‐time should be on the order of the diffusion‐time constant and that the deposition time should be smaller than the diffusion time constant. Reverse current, i.e., dissolution, is shown to play an important role in diminishing void size. Comparison with two‐dimensional calculations indicates that the theory is an adequate yet efficient means of simulating shape change.

Ionized physical vapor deposition of integrated circuit interconnects

Interconnects, once the technological backwater of integrated circuit technology, now dominate integrated circuit cost and performance. As much as 90 percent of the signal delay time in future integrated circuit designs will be due to the interconnection of semiconductor devices while the remaining 10 percent is due to transistor-related delay. This shifts the thrust of critical research toward an improved understanding of interconnect science and technology. Shrinking circuit geometries will require high aspect ratio (AR) vias to interconnect adjacent metal layers. By the year 2007 it is predicted that logic circuits will use 6 to 7 interconnected metal layers with via ARs of 5.2:1. Memory will need fewer layers, but ARs as high as 9:1. In this paper, the demands of interconnect technology will be reviewed and the opportunities for plasma-based deposition of vias will be discussed. One promising new method of fabricating high-aspect ratio vias is ionized physical vapor deposition (I-PVD). The technique economically creates a unidirectional flux of metal which is uniform over 200–300 mm diameter wafers. Since metal ejected by conventional sputtering is primarily neutral and exhibits a cosine angular velocity distribution, sputtered metal atoms do not reach the bottom of high AR vias. By sputtering these atoms into a moderate pressure (4 Pa), high-density Ar plasma, however, the metal atoms are first thermalized and then ionized. The ions are then readily collimated by the plasma sheath and directionally deposited into narrow, deep via structures. Experiments have consistently shown that over 80% of the metal species are ionized using I-PVD. The physical mechanisms responsible for ionization will be discussed from both an experimental and modeling perspective and the spatial variation of metal ionization is experimentally determined.

Reemission of sputtered refractory metals during deposition

Refractory metals are of interest for use in diffusion barriers and adhesion layers in ultra-large-scale integrated circuit metallization. An interesting feature of many of these materials is the reemission of some of the deposited flux during sputtering. This can be useful in depositing conformal layers in high aspect ratio contacts and vias. Overhanging structures have been used to study reemission in TiW, Ti, Nb, W, Ta, and Pt sputtering. While Ti and Nb show negligible reemission under typical sputtering conditions, Ta, W, and Pt show noticeable film deposition in regions obstructed from direct flux. TiW alloy sputtering shows evidence of the largest amount of reemitted flux. Sputtering conditions from 5 to 15 mT with power densities from 10 to 35 W/cm2 were studied, without significant change in the reemission flux. Variation of substrate temperature and moderate substrate bias was also not found to cause a measurable change in the reemission characteristics.

Antenna sputtering in an internal inductively coupled plasma for ionized physical vapor deposition

Ionized physical vapor deposition (IPVD) is an emerging technology for coating high aspect ratio vias and trenches for the microelectronics industry. Ionized physical vapor deposition systems typically utilize an inductive discharge generated by an internal antenna. Because the antenna is immersed in the plasma, the possibility of antenna material sputtering into the discharge is a contamination issue. In this investigation, optical emission spectroscopy is used to acquire spectra from an IPVD system to monitor the presence of antenna metal in the discharge. The observed presence of antenna material in the spectra confirms that antenna sputtering is occurring. Experimental sputter rates as determined from witness plate observations are in reasonable agreement with predictions of a simplified model of antenna sputtering, indicating that the sputtering results from large self-bias voltages on the rf antenna.

Low temperature AlCu planarization by PVD AlCuGe alloys: Invited lecture

This paper describes a low temperature reflow of AlCU alloys by incorporating Germanium in the film. Germanium is added in AlCu alloys by reacting GeH 4 with the films. The Al-alloy reflow occurs due to formation of low melting point eutectic with Germanium. This technique results in a low cost process for filling high aspect ratio vias/lines with Al-based alloys with improved damascene capability. This is achieved at temperatures below 400°C by reacting Germane (GeH 4) with AlCu alloys deposited by conventional techniques which result in voids, gaps and poor filling. Using such a process it is demonstrated that high aspect ratio vias with large undercuts can also be filled without voids. Also it is possible to partially fill the vias with low pressure sputtering followed by Germane reactions. This reaction eliminates overhangs and fills vias with AlCuGe. The low temperature provides the capability to form a multilevel homogeneous Al-alloy via/line structure without degrading the resistance of underlying interconnects. The reliability data shows that AlCuGe via/interconnect structure deposited by this method is at least “1.5X” better electromigration life time ( t 50) to that of hot sputtered AlCu (deposited at 535°C) and almost “2X ” to that of conventionally used CVD W stud/AlCu interconnect structure. The improvement in the reliability may be attributed to filling without voids high aspect ratio sub-half micron vias with low resistivity metal such as AlCuGe at temperatures well below 400°C. Since this technique does not rely on the wetting layer or the diffusion barrier a lower sheet resistance of AlCuGe line is achieved compared to high temperature reflow processes. Also the reaction between Al and GeH 4 takes place uniformly resulting in reproducible contact resistance. Most importantly it is possible to achieve “high open-short yields” of comb-serpentine structures, and via chains of difficult to polish materials like AlCu using a “damascene” process.

Effects of aluminum sputtering process parameters on via step coverage in micro-electronic device manufacturing

It has been observed that the step coverage achieved for aluminum deposition at 200°C on a multi-chamber (ultra-high vacuum) horizontal physical vapor deposition (PVD) system (System A) is electrically comparable to the step coverage on a single chamber, high vacuum (vertical) PVD system (System B) at 300°C under the optimized conditions of pre-clean process, sputtering power, argon pressure and chamber hardware configuration. In addition, it has been determined that the metal step coverage is relatively poor at temperatures higher than 200°C on System A, whereas the metal step coverage on System B is better at 300°C when compared with both substantially lower and higher temperatures. Since step coverage is a vital parameter in the manufacturing of sub-micron devices with high aspect ratio vias, the effect of the sputtering process parameters has been studied. This work investigates possible causes for the observed temperature effect and evaluates possible methods for improving the step coverage. The directionality of sputtering and film-substrate bonding are identified as two primary factors controlling step coverage.

Carrier-gas effects on characteristics of copper chemical vapor deposition using hexafluoro-acetylacetonate-copper (1) trimethylvinylsilane

The deposition characteristics of copper chemical vapor deposition using the liquid precursor hexafluoro-acetylacetonate-copper (1) trimethylvinylsilane are investigated. The precursor supply is directly controlled by a liquid-injection system. The deposition rate and selectivity on the substrate surface strongly depend on the carrier gas. A hydrogen carrier-gas system has a higher deposition rate and lower selectivity than an argon carrier gas. The deposition rate of copper is proportional to the square root of the precursor partial pressure under reaction-rate-limited conditions at a substrate temperature below 200 °C. In these conditions, a deposition rate of up to 70 nm min −1 and an apparent activation energy of 11 kcal mol −1 has been obtained. Surface morphology and step coverage improves with decreasing substrate temperature and increasing precursor supply. A smooth film with a low resistivity of 2.0 Ω cm can be formed superconformally on the step coverage at a substrate temperature below 180 °C and a high aspect ratio vias can be filled under the optimum deposition conditions.

Vlsi Metallization by Coherent Magnetron Sputtering

Magnetron sputtering has been used extensively to deposit interconnect layer, diffusion barrier layer, adhesion layer and anti-reflection layer in semiconductor production. As the dimension of VLSI devices get smaller, it is becoming increasingly difficult to deposit these metal layers into high aspect ratio contacts and vias using conventional sputtering method. Coherent sputtering, where a perforated plate (collimator) is placed between the sputtering target and wafer, improves bottom coverage and step coverage. In the recent years, coherent sputtering has been used to deposit titanium, titanium nitride and aluminum films. However, the existence of collimator changes the deposition processes and properties of the deposited films. In this article, we will discuss some of the properties of coherent deposition.

Void formation in pulsed laser induced via/contact hole filling

Metal (Au, Cu, and Al-1% Cu) layers sputter deposited over vias and contact holes of varying diameter and aspect ratio are melted and planarized by irradiation with either a 600 ns pulse duration flashlamp-pumped dye laser or a 35 ns pulse duration excimer laser. High aspect ratio (≳1) vias and contact holes yield metal profiles that suffer from void formation during the laser-induced flow. This void formation is explained by considering surface tension forces that, in high aspect ratio cases, act to close off the top of a hole without filling it.

Submicron two-layer metal system of selective tungsten and TiW cap metallization

The processing options available to fabricate multilevel metal interconnects are becoming greatly reduced as circuit dimensions enter the submicron regime. Advanced lithography techniques are required, such as x ray, electron-beam, or monochromatic steppers. The choice of metal materials is small, due to resistivity and interconnect dimension requirements. Sputter deposition equipment has difficulty in depositing the metal into the high aspect ratio vias and new processes with superior stepcoverage are required. Other processing technologies are also experiencing difficulties as dimensions shrink. This paper discusses the utilization of certain advanced processing technologies, namely: stepper lithography, TiW capped AlCu metallization, chemical vapor deposition (CVD) tungsten, plasma deposited oxide (tetraethylorthosilicate source), and etchback planarization to successfully fabricate a submicron two-layer metal structure. The test vehicle had via chains increasing in length from 10–8000 vias with dimensions from 0.75–1.5 μm. Serpentine metal patterns ranged from 0.001–1.1 m in length with pitch of 1.75–3.0 μm. Fabrication issues and potential solutions, as well as electrical data obtained from the test vehicle are presented. The electrical data includes metal serpentine yield and via chain data, comparing: (1) warm deposited AlCu, (2) hot deposited AlCu, and (3) CVD tungsten filled vias.

Substrate Heating Effects in Excimer Laser Planarization of Aluminum

ABSTRACTSubstantial improvements in excimer laser planarization processes are observed with substrate heating. Cavities, associated with filling of high aspect ratio vias at low substrate temperature, can be eliminated by substrate heating. Damage associated with pulse overlap regions can be temperature sensitive, and is reduced as substrate temperatures areincreased. While required fluences for planarization and sample damage both decrease as the sample temperature increases, the relative insensitivity of the damage threshold generally results in larger process windows at higher temperatures. We also report model calculations of the effect of substrate heating on sample temperature distributions and the durations of the laser driven melts.