Aspect Ratio Trapping Research Articles

Liquid Phase Epitaxy (LPE) Formation of Localized High Quality and Mobility Ge & SiGe by High Dose Ge-Implantation with Laser Melt Annealing for 10nm and 7nm Node CMOS Technology

Localized Ge and SiGe high quality/mobility device surface material region on bulk-Si and SOI wafers are needed for 10nm and 7nm node CMOS technology. Traditionally SiGe and Ge device surface material on bulk-Si or SOI wafers are realized by CVD epitaxial growth or Vapor Phase Epi (VPE) at elevated temperatures. Selective deposition can be achieved with hard mask. To reduce defects strain relaxed buffer (SRB) or aspect ratio trapping (ART) have been employed with bulk-Si or layer transfer wafer bonding for SiGeOI or GeOI. An alternative to VPE is to use either SPE (solid phase epitaxy) or LPE (liquid phase epitaxy) to form SiGe or Ge epitaxial surface layers. Using high dose Ge implantation >E16/cm2 with photoresist soft mask as proposed in 2004 by Borland et al [1,2]. Localized amorphous Ge surface regions can be formed after Ge-infusion doping by Gas Cluster Ion Beam (GCIB) technique followed by low temperature SPE to form single crystal thin surface Ge epitaxial layers but residual end-of-range (EOR) damage remained. Today, laser melt annealing of implanted junctions are currently being used in production for high quality back-side illuminated CMOS image sensors used in smart phone cameras by several IC and foundry semiconductor manufacturers to completely eliminate any residual implant damage/defects with 100% dopant activation provided the melt depth exceeds the implant damage depth [3]. Last year at IWJT-2013 Borland et al [4] reported using Ge-plasma ion implantation at 1E16/cm2 and 1E17/cm2 doses with laser melt annealing to realize up to 55% SiGe by LPE with >4x higher mobility at 160cm2/Vs. One limitation they noted with plasma implantation was poor retained dose due to surface sputtering at low energies which limited the Ge content to <55% for 1E17/cm2 dose. Therefore to overcome this retained dose problem we investigated Ge beamline ion implantation in this paper which should give 100% retained dose. The Ge surface amorphous layer thickness measured by elipsometry was 15nm while the Ge-SIMS depth profile measures 7nm Ge at 100%. Therma-wave analysis was used to monitor the Ge-implant damage recovery and Ge or SiGe recrystallized epitaxial surface layer after various laser melt annealing conditions of varying power level and pulse duration. The Ge-SIMS depth profiles shows we could vary the melt depth for LPE Ge layer from 10nm to >400nm and the Ge layer content from 97% down to 2% respectively. We will also show X-TEM of the Ge-LPE regions. Sb implantation was used to investigate n-type dopant activation in Ge at low and high doses of 3E13/cm2 and 3E15/cm2. Rs measurements were done using a special Hx 4 point probe and SRP (spreading resistance profile) depth profiles. In summary, using high dose beam-line Ge-implantation we realized >7nm amorphous Ge deposition. Epitaxial growth of Ge was achieved by liquid phase epitaxy using shallow laser melt annealing between 10nm and >400nm melt depths.

Lateral Gemanium Growth for Local GeOI Fabrication

Ge is a very attractive material for optoelectronic applications and for future CMOS technologies. Therefore the creation of Ge on Si with low defect density is of great interest. Several techniques to grow high quality Ge on Si are reported e. g. in combination with cyclic annealing and etching (1, 2) or using the aspect ratio trapping technique (3). In this study, the fabrication of local GeOI structures is demonstrated by filling a lateral cavity which was formed by selective sidewall etching (4) of a mesa-patterned SiO2 / Si layer on a SOI wafer. Lateral Ge growth is carried out by using a single wafer reduced pressure CVD system. For sample preparation, epitaxial Si is deposited. The thickness of the Si on buried oxide (BOX) is targeted to 430 nm. Then wet oxidation for 300 nm is performed to produce a 300 nm thick SiO2 cap on top of 300 nm thick Si on the BOX. Top SiO2 and Si on BOX are removed by RIE dry etching to form lateral Si (010) or Si (110) surfaces at the sidewall of a mesa structure. After that, the wafer is cleaned by standard HF-last RCA cleaning. The wafer is loaded into the epi. chamber and baked at 850oC in H2 to remove residual oxide on the Si sidewalls. Then selective etching of Si by HCl is performed to form a cavity in the SiO2. After the HCl etching, Ge is deposited selectively using a H2-GeH4-HCl gas mixture. SEM is used for characterization of the deposited Ge and TEM is applied for dislocation analysis. The strain distribution is analyzed by micro Raman spectroscopy at 514 nm laser wavelength. An angle view SEM image of the sample after HCl etching is shown in Fig. 1. By HCl etching Si between the BOX and the SiO2 cap is laterally removed. The thickness loss of the BOX and the SiO2 cap are negligible indicating that the Si etching process is highly selective to SiO2. No bending is observed at the floating part of the SiO2 cap layer. At the etchfront a Si (111) facet is formed by the lateral HCl etching. A cross section TEM image of the sample after HCl etching and selective Ge growth is shown in Fig. 2. The Ge layer is selectively grown laterally on the Si surface in the cavity formed by the HCl etching. Dislocations are densely located near the interface between Si and Ge. Aspect ratio trapping (3) also works for the lateral direction, resulting in a high crystal quality Ge layer growth after ~200 nm. In Figure 3, an AFM amplitude image of a 5 µm square mesa structure with [010] sidewall direction is shown after HCl etching and lateral Ge growth followed by the removal of the SiO2 cap by HF dip. The interface between Si and Ge is visible. The root mean square of the Ge surface roughness is ~0.4 nm. It is defined by the interface roughness between Si and the SiO2cap layer. In Figure 4, a plan-view TEM image of a 5 µm square mesa structure after HCl etching and lateral Ge growth is shown. A (113) facet is observed at the growthfront of Ge. Dislocation networks are located near the Si interface. Stacking faults run only parallel or perpendicular to the [110] direction. Between them a wide area without any dislocations toward the [010] direction is observed. These results demonstrate the feasibility of the fabrication of local GeOI with high crystal quality by an additional lithography and an etching process. References 1) Y. Yamamoto et al., Solid-State Electronics 60 (2011) 22) Y. Yamamoto et al., Thin Solid Films 520 (2012) 32163) J. S. Park et al., Appl. Phys. Lett. 90 (2007) 0521134) Y. Yamamoto et al. Thin Solid Films 517 (2008) 90

Invited; First-Principles Studies of the Defect Formation in III-V FETs Grown by Fin Replacement Method

Introduction III-V fin-shaped field-effect transistors (FinFETs) are considered to be attractive candidates for high-performance n-type FETs, thanks to both the light electron effective mass and to the improved electrostatic control. III-V FinFETs integrated on a Si substrate are advantageous with respect to their cost effectiveness. Aspect Ratio Trapping (ART) is one of the possible integration roads to be followed to achieve the growth of non-silicon channels on a Si substrate by reducing the density of defects obtained in the filled trenches [1]. In the ART process, the III-V fin is grown inside trenches of SiO2by using a metal organic vapor phase epitaxy (MOVPE) process, which implies that the precursors interact not only with the semiconductors but also with the oxides. The reaction of the precursors with the oxides could lead to the formation of defects around the interface which could be responsible for the degradation of the electrical reliability of III-V FinFETs. In this study, we report the evaluation of the formation of defects due to the reactions between the precursors and the oxides using first-principles simulations. Methodology The formation enthalpies [2] of the defects are calculated using the Quantum Espresso package [3] based on density functional theory. The lower the formation enthalpy is, the more likely the reaction is to occur. We used the Perdue-Burke-Ernzerhof exchange-correlation potential [4] combined with ultrasoft pseudopotentials to compute the energetics of the reactions. The charge states of the defects are assumed to be neutral. One of the considered reactions consists into the formation of interstitial defects in SiO2 due to the diffusion of the III-V components and of the doping atoms from the precursors. The list of considered precursors and oxides are summarized in Table 1. Mg and Zn could be used as acceptor doping sources for the III-V compounds. For the SiO2, an amorphous model is used, built from classical molecular dynamics simulations with the LAMMPS package [5]. Results and Discussion Fig. 1 shows the calculated formation enthalpies. For the precursors, we also envisaged some intermediate atomic configurations that correspond to the transition products active during the MOVPE process. Our simulations show that the initial states of the precursors have high formation enthalpies, indicating that there is no driving force to promote the diffusions of the III-V elements and of the dopants into the STI. However, as the growth proceeds and that the precursors begin losing their organic ligands, the formation enthalpies are significantly reduced. Zn and Mg have the lowest formation enthalpies of all of the reactants considered, which suggests that the diffusion of doping sources into SiO2 could be favored. In order to confirm the latter for the Mg case, secondary ion mass spectrometry measurements (SIMS) were performed on a SiO2 blanket exposed to the Mg-precursors (see Fig. 2). The diffusion of Mg is clearly observed near the SiO2surface, which is consistent with the theoretical picture (Fig. 1). In order to prevent these defect-related issues, it will be important to understand a risk of formation of defects using the ab initio approaches. Acknowledgment This work has been supported by the IMEC core partners and IMEC Industrial Affiliation Programs (IIAP).

Invited: Wafer Bonding: An Integration Route for Hybrid III-V/SiGe CMOS on 300mm

1. Introduction As Si-CMOS scaling is becoming increasingly challenging, III-V compound semiconductors such as InxGa1-xAs (x≥0.53) (InGaAs) are receiving an increasing interest as channel material for nFET [1,2]. Together with SiGe as a pFET channel, they are considered as potential candidates to replace silicon for low power, high performance CMOS thanks to their better transport properties. A prerequisite in view of integration at VLSI scale is the formation of high quality III-V heterostructures on a silicon substrate to enable production on large size wafers.III-V integration on Si by direct wafer bonding is considered as one of the possible paths towards this objective [3]. Our rationale is that (1) InGaAs-on-insulator can be fabricated with the appropriate critical dimensions and thermal stability, (2) source wafers can be fabricated on large diameter wafers with acceptable defect densities and (3) hybrid substrates can be used to fabricate simple CMOS circuits. 2. InGaAs-on-Insulator A possible fabrication path for InGaAs-On-Insulator substrate is summarized. For demonstration purposes, the source substrate can simply be etched. A manufacturable process will however rely on the H-induced thermal splitting, as demonstrated in [3]. For thin layers as required for advanced CMOS, the thickness of InGaAs-o-I is below the critical value determined by the thermal strain up to 600°C. In addition, the interface energy at the Al2O3-Si bonding interface is almost 1 J/m2, larger than the one determined for SiO2-Si bonding in SOI wafers [4]. Such structures can therefore undergo high temperature processes such as the regrowth of highly doped InGaAs source and drain. The thermal stability is illustrated by showing that the regrowth of InGaAs do not degrade the structural quality of the underlying ultra-thin InGaAs-o-I. Functional self-aligned devices have been processed down to short gate length Lg=24nm, demonstrating the stability of such structures [5]. 2. Large diameter source wafer For VLSI integration, the bonding flow must be available for large diameters. As no InP substrate is available above 4”, the only possibility is to grow a virtual donor wafer onto a large diameter silicon substrate. Low defect density as well as very low roughness is required. In our internal work, GaAs deposition is performed by MBE on 200mm Ge/Si (001) substrate 6° off-cut, and subsequent pseudomorphic InxAl1-xAs grading buffer (x~ 0-0.65) allows reaching InP lattice-matching conditions. The formation of a thin InGaAs active layer completes the heterostructure that is compatible with the direct wafer bonding process. The best rms/TDD values reported so far are for GaAs 1nm/low-107cm-2 , and for InGaAs 2nm/mid-108cm-2. , close to the best value reported so far for Aspect Ratio Trapping methods. Excellent device metrics have been obtained on such heterostructures, supporting the idea that they can be used as donor wafers. 3. Hybrid circuits Based on the previous results, the co-integration of fully depleted InGaAs and SiGe MOSFETs can be envisioned. Starting from an 8 nm thick ETSGOI wafer, a 6 nm thick InGaAs layer can be transferred as in [6]. Because of the low temperature used during wafer bonding, and due to the presence of the BOX, cross-diffusion between InGaAs and SiGe is inhibited. The n- and p- active regions are defined based on mesa definition in the InGaAs and SiGe layer. The rest of the process follows an ETSOI-like front-end where n- and p-FETs are processed simultaneously. Such an hybrid structure is shown, for which a simplified process has been utilized, including a common gate stack and metal source drain instead of raised source/drain. The device characteristics have been extensively reported in [6], and a typical inverter transfer characteristic has been obtained, leading to the first demonstration of hybrid CMOS circuits based on high mobility channels.[1] J. Lin, D. A. Antoniadis and J. A. Del Alamo, IEDM Tech. Dig. (2012)[2] M. Radosavljevic, G. Dewey, D. Basu, J. Boardman, B. Chu-Kung, J. M. Fastenau, S. Kabehie, J. Kavalieros, V. Le, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, L. Pan, R. Pillarisetty, W. Rachmady, U. Shah, H. W. Then and Robert Chau, IEDM Tech. Dig. (2011)[3] L. Czornomaz, N. Daix, D. Caimi, M, Sousa, R. Erni, M. D. Rossell, M. El-Kazzi, C. Rossel, C. Marchiori, E. Uccelli, M. Richter, H. Siegwart and J. Fompeyrine, IEDM Tech. Dig. (2012)[4] N. Daix, L. Czornomaz, D. Caimi, C. Rossel, M. Sousa and J. Fompeyrine, S3S conference 2013[5] L. Czornomaz, et al., Proc. ESSDERC 2013[6] L. Czornomaz, et al., IEDM Tech Digest (2013)

Low defect InGaAs quantum well selectively grown by metal organic chemical vapor deposition on Si(100) 300 mm wafers for next generation non planar devices

Metal organic chemical vapor deposition of GaAs, InGaAs, and AlGaAs on nominal 300 mm Si(100) at temperatures below 550 °C was studied using the selective aspect ratio trapping method. We clearly show that growing directly GaAs on a flat Si surface in a SiO2 cavity with an aspect ratio as low as 1.3 is efficient to completely annihilate the anti-phase boundary domains. InGaAs quantum wells were grown on a GaAs buffer and exhibit room temperature micro-photoluminescence. Cathodoluminescence reveals the presence of dark spots which could be associated with the presence of emerging dislocation in a direction parallel to the cavity. The InGaAs layers obtained with no antiphase boundaries are perfect candidates for being integrated as channels in n-type metal oxide semiconductor field effect transistor (MOSFET), while the low temperatures used allow the co-integration of p-type MOSFET.

(Invited) Material Engineering for 7nm FinFETs

Recently, several enabling technologies have become available for integrating non-Si channels on Si wafers, including HKMG with acceptable trap densities, aspect ratio trapping, and low temperature epitaxy with in-situ doping. This considerably broadens the list of potential candidate materials for the 7nm technology node in search of exceeding performance of Si FinFETs.The search for the alternative channel materials is often motivated by high levels of carrier mobility in bulk material. Some promising demonstrations have been done with long channel transistors. However, the bulk carrier mobility is not relevant for performance of the short channel transistors. The target channel length for the 7nm node is about 15 nm, with most of the carriers exhibiting ballistic transport without experiencing scattering events when moving from source to drain. The ballistic transport favors materials with lighter effective carrier mass in terms of the driving current strength. On the flip side, such materials exhibit higher off-state leakage currents via band-to-band tunneling and direct source-to-drain tunneling mechanisms. So, instead of being guided by the bulk carrier mobility numbers, a more appropriate approach is to evaluate the trade-off between the on-state and the off-state current levels for the particular combination of material properties and transistor design rules.In this work, we assume that the process-related issues such as defects can be resolved over time and focus on performance of defect-free materials, with performance determined by fundamental material properties. This way, we can get the upper bound on performance for each candidate material and see if it is worth pursuing in terms of struggling through laborious process integration.Besides the on-state and off-state currents, several other key metrics are included into the trade-off analysis, such as self-heating and the ability to withstand and dissipate the heat, and parasitic R and C of the MOL.The comparative analysis of several candidate channel materials is performed considering four technology flavors: HP, SP, and LP logic, and the I/O transistors. The appropriate modeling methodologies are introduced to cover these materials and the target design rules.

Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping

We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =-0.5 V, good short-channel effect control, and high transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> =1.2 mS/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =-1 V and 1.05 mS/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =-0.5 V for L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.

High-resolution electrical and chemical characterization of nm-scale organic and inorganic devices

Almost ever since the advent of the microelectronics adventure, silicon-based MOSFET (metal–oxide–semiconductor field-effect transistor) technology has been largely dominant. However, for a few years now this technology has exhibited some fundamental limitations in tackling the increasingly challenging issues of miniaturization and improvements in processing speed and power consumption. Hence, new inorganic semiconductor materials (Ge, InGaAs, InP, InSb, GaN, GaSb, SiC, etc.) and new architectures (multiple-gate FETs, nanowire T-FETs, etc.) are being progressively introduced. These new materials are mainly introduced due to their increased mobility (to boost the processing speed of the devices), and the new architectures are required to reduce the junction leakage (and hence reduce the power consumption). These architectures are typically three-dimensional, and with the continuous decrease of dimensions, they also represent extremely confined volumes in which statistical and quantum effects start to play an increasing role. The entirely successful application of these new materials and architectures towards realizable technologies is facing some challenges. The most significant one is probably the impact of defects linked to growth processes and to the presence of stress. Indeed, the presence of different semiconductor materials with different lattice dimensions leads to crystalline defects, threading dislocations, and microtwins that affect the diffusion of dopants and the material mobility (due to scattering). When growth is performed in narrow trenches, dislocations are trapped within the confined volume (aspect-ratio trapping) and, theoretically, defect-free layers can be obtained. However, even if an apparently defect-free layer is obtained, the polar nature of the complex compound materials implies that antiphase boundaries can still be formed, which potentially represent important charge and recombination centers. Beyond the standard logic/memory applications there is a very strong increase in “More than Moore” developments targeting energy (photovoltaic, energy storage), imaging (e.g., quantitative medical imaging), sensor/actuators linked to CMOS-base circuitry, biochips, etc. The utilization of graphene in order to process high mobility (both for holes and electrons) field-effect transistors is also being intensively studied. In all these cases, metrology is a challenge, and no universal solution is identifiable. Moreover in many cases it becomes also very difficult to establish a complete assessment of accuracy, precision and spatial resolution due to a lack of appropriate 3-D standards and comparative metrology. The development of high-performance devices (high speed and density, low consumption) is not the only objective of the electronic industry. The need for low-cost devices processed industrially on flexible and light substrates over very large surfaces has led to the emergence of electronic components based on organic semiconductors. The organic materials used nowadays are typically made of single molecules in highly ordered assemblies or of polymeric semiconductors in thin films. In recent years, an extensive set of organic-based prototypes (transistors, sensors, electrochromic devices, biosensors, photodiodes, photovoltaic cells, etc.) have been developed, demonstrating the strong potential of these materials. However, the advent of commercial applications often requires important breakthroughs towards more efficient and stable organic photovoltaic devices. This implies reduced exciton diffusion lengths (and thus more efficient collection) through the fabrication of an entangled mixture of the acceptor–donor layers, the addition of light scattering nanoparticles or metallic nanoparticles (spectrum harvesting through plasmonics) in the active layer or even wavelength convertors based on metal nanoparticles with a dye to shift the wavelengths. Improving the lifetime of organic solar cells requires incorporating optically transparent inorganic barriers in between the polymer films to prevent moisture penetration. Unfortunately, these organic systems represent an even more challenging metrological problem as compared to their inorganic counterparts, as it no longer suffices to determine the atomic and electrical distributions, but one is also faced with the additional, equally important problem to trace, on the nanometer scale, the chemical configuration and the polymeric information. It is therefore important to develop and improve two- and three-dimensional characterization techniques that can be utilized on both organic and inorganic semiconductors. These techniques should allow determination of the carrier/dopant distribution with an excellent sensitivity and repeatability (within 3 to 5%) with nanometer spatial resolution (subnanometer in inorganic and below 10 nm in organic) over a broad dynamic range (up to five decades). Ideally, they should also be able to probe the elemental distribution and to provide information on chemical bonding. In this Thematic Series, we present the work of various leading labs in developing such techniques. Targeting 2-D/3-D resolution, one inevitably needs to look at scanning probe techniques that can be proclaimed to be dominant for electrical characterization and atomic probes that can be viewed as the ultimate in terms of compositional analysis. At the same time we need to recognize that, notwithstanding the past efforts and achievements, there remains a considerable knowledge and performance gap between the state-of-the-art metrology and the future metrology requirements. Hence also some simulation work is presented in this Thematic Series. Pierre Eyben Leuven, April 2013

(Invited) Aspect Ratio Trapping: A Unique Technology for Integrating Ge and III-Vs with Silicon CMOS

This paper describes the recent development of the Aspect Ratio Trapping (ART) heterointegration technique. This technique uses high aspect ratio sub-micron trenches to trap threading dislocations, greatly reducing the dislocation density of lattice mismatched materials grown on silicon. ART is shown to be very effective for a wide variety of materials including Ge, GaAs and InP. It has been combined with epitaxial lateral overgrowth to create long, 18 micron wide strips of low dislocation density material. ART has been used to integrate many types of Ge and III-V devices on silicon including GaAs MOSFETs, GaAs lasers, GaAs tunnel diodes and a silicon infrared imager chip with monolithically integrated Ge photodiodes.

Aspect Ratio Trapping: A Unique Technology for Integrating Ge and III-Vs with Silicon CMOS

not Available.

Selective epitaxial growth of Ge(1 1 0) in trenches using the aspect ratio trapping technique

The aim of this study was to assess the efficiency of aspect ratio trapping in improving the crystalline quality of relaxed Ge(1 1 0) layers selectively grown in trenches surrounded by SiO 2. The 400 °C growth of a few hundreds of nanometers thick Ge layers has first been studied on blanket Si(1 1 0) surfaces then in recessed areas of Si(1 1 0) patterned wafers. The influence of 1 min H 2 anneals (in-between 600 and 850 °C) on the surface morphology, crystalline quality and strain state of blanket Ge(1 1 0) layers has notably been quantified. Intermediate annealing temperatures (750 °C) have improved the crystalline quality and increased the macroscopic strain relaxation of those layers, without too high a surface roughening. (1 1 0) Si windows (surrounded by shallow trench isolation) of patterned wafers have then been recessed by ≈300 nm using gaseous HCl, with a definite faceting and a slight roughening of the resulting cavities. Epitaxial lateral overgrowth of Ge has then been implemented in those trenches, followed by 1' H 2 bakes at 750 °C. Chemical mechanical polishing has been used afterwards to get rid of the several hundreds of nm thick Ge layer overflowing on the SiO 2 areas (very reduced dishing and flat Ge(1 1 0) surfaces obtained in the end). The efficiency of aspect ratio trapping in reducing the defect density in those Ge(1 1 0) layers is not obvious. Indeed, some trapping of inclined defects in the SiO 2 sidewalls of narrow Ge(1 1 0) patterns (∼80 nm long) has been evidenced. However, the theoretically unexpected appearance of defects at 90° to the surface (i.e. normal to (1 1 0)) that were consequently not trapped was detrimental to defect density reduction. Those 90° defects may have arisen from interactions of inclined defects with one another. The reduction of the high defect density in relaxed (1 1 0) layers is thus still challenging and requires further investigations.

A complex x-ray structure characterization of Ge thin film heterostructures integrated on Si(001) by aspect ratio trapping and epitaxial lateral overgrowth selective chemical vapor deposition techniques

The development of Ge thin film substrates with low defect densities is of interest for future microelectronics as well as photovoltaics. This paper presents a complex x-ray characterization of Ge heterostructures, which were integrated on patterned Si(001) substrates using “aspect ratio trapping (ART)” and “epitaxial lateral overgrowth (ELO).” In both cases, thermal SiO2 layers were patterned into trenches with appropriate aspect ratio to confine misfit dislocations. In the case of ART Ge thin films grown in 180 nm spaced trenches, the x-ray characterization reveals that the Ge coalescence process between neighboring growth windows must be carefully controlled to avoid defect generation. In the case of ELO Ge heterostructures grown from trenches spaced by 20 µm, coalescence effects are clearly reduced but complications are detected in the form of lattice plane tilt in the ELO wings. Simulations are applied to unveil the influence of the different thermal expansion coefficients of Ge, Si, and SiO2 on the strain status of the ART and ELO Ge heterostructures.

Monolithic Integration of GaAs/InGaAs Lasers on Virtual Ge Substrates via Aspect-Ratio Trapping

GaAs/InGaAs quantum-well lasers have been demonstrated by metallorganic chemical vapor deposition on virtual Ge substrates on Si via aspect-ratio trapping (ART) and epitaxial lateral overgrowth (ELO). Laser-structure growth is achieved in two steps: The first step is growing uncoalesced defect-free Ge stripes on a trench-patterned silicon substrate via ART, whereby the misfit defects originating from the Ge/Si interface are trapped by laterally confining sidewalls. Defects arising from above the film are reduced by using an optimized ELO process followed by chemical mechanical polishing to provide a planar Ge surface. The second step is overgrowing a GaAs/InGaAs laser structure on the virtual Ge substrate. A number of GaAs/Ge integration issues, including Ge autodoping and antiphase domain defects in GaAs, have been overcome. Despite unoptimized laser structures with high series resistance and large threshold current densities, pulsed room-temperature lasing at a wavelength of 980 nm has been demonstrated using a combination of ART and ELO. This technique is very promising for the achievement of reliable GaAs-based optoelectronic devices on Si.

Growth and characterization of GaAs layers on polished Ge/Si by selective aspect ratio trapping

Epitaxial GaAs layers have been deposited on polished Ge film grown on exactly (0 0 1) oriented Si substrate by metal-organic chemical vapor deposition (MOCVD) via aspect ratio trapping (ART) method. Double-crystal X-ray diffraction shows that the full-width at half-maximum (FWHM) of the (4 0 0) reflection obtained from 1 μm GaAs is 140 arcsec. Scanning electron microscopy (SEM) of the GaAs layer surface shows that the amount of antiphase domain defects (APD) raised from GaAs/Ge interface using Ge ART on Si is dramatically reduced compared to GaAs layers grown on exact (0 0 1) Ge substrate. Defect reduction and Ge diffusion at vicinal GaAs/Ge interface were investigated via cross-section transmission electron microscopy (X-TEM) and secondary ion mass spectrometry (SIMS). Film morphology and optical properties were evaluated via SEM and room temperature photoluminescence (PL).

Thin Film InP Epitaxy on Si (001) Using Selective Aspect Ratio Trapping

High quality InP thin films have been demonstrated in SiO2 trenches on silicon via Aspect Ratio Trapping (ART), whereby defects arising from lattice mismatch (~8%) are trapped by laterally confining sidewalls. Double-buffer layers and two-step ART growth processes have been employed to trap vertical threading dislocations originating at InP/Si interface. InP film quality and optical properties have been analyzed using SEM, TEM and room temperature photoluminescence. Full trapping of dislocations has been demonstrated for trenches up to 400 nm in width without the additional formation of defects at the sidewalls above 500 nm initial growth. This approach shows great promise for the integration of III-V materials onto silicon.

Fabrication of Low-Defectivity, Compressively Strained Ge on Si0.2Ge0.8 Structures Using Aspect Ratio Trapping

Low-defectivity, compressively strained Ge on was fabricated in oxide trenches using the aspect ratio trapping technique. This was accomplished through the use of pre-epi bakes optimized to remove interfacial impurities which can lead to defective epi layers. Pre-epi bake over the optimum temperature caused the release of stored elastic strain energy in the regions leading to undesirable undulations of the layers. Using the optimum prebake at , thick, compressively strained Ge was grown. It had 1 and 0.45% elastic strain along and perpendicular to the trench direction, respectively, which is well-suited for strained Ge channels in future complementary-metal-oxide semiconductor devices.

Low-Defect-Density Ge Epitaxy on Si(001) Using Aspect Ratio Trapping and Epitaxial Lateral Overgrowth

Low-defect-density Ge epitaxy was fabricated using aspect ratio trapping combined with epitaxial lateral overgrowth techniques. Dislocations from the Ge/Si interface were trapped inside oxide trenches, and then Ge was laterally grown to form 20 μm wide, 6 mm long strips. Chemical mechanical polishing of Ge was used to planarize the faceted strips. Uncoalesced Ge strips showed a defect density as low as 1.6 X 10 6 cm -2 from plan-view transmission electron microscopy, while coalesced Ge had higher defect density. This approach shows great promise for the integration of low-defect-density Ge and III-V materials on Si.

Atomic-layer-deposited Al2O3/GaAs metal-oxide-semiconductor field-effect transistor on Si substrate using aspect ratio trapping technique

High quality GaAs epilayers grown by metal-organic chemical vapor deposition are demonstrated on a SiO2-patterned silicon substrate using aspect ratio trapping technique, whereby threading dislocations from lattice mismatch are largely reduced via trapping in SiO2 trenches during growth. A depletion-mode metal-oxide-semiconductor field-effect transistor (MOSFET) is demonstrated on a n-doped GaAs channel with atomic-layer deposited Al2O3 as the gate oxide. The 10 μm gate length transistor has a maximum drain current of 88 mA/mm and a transconductance of 19 mS/mm. The surface mobility estimated from the accumulation drain current has a peak value of ∼500 cm2/Vs, which is comparable with those from previously reported depletion-mode GaAs MOSFETs epitaxially grown on semi-insulating GaAs substrates.

Chemical Mechanical Polishing of Epitaxial Germanium on SiO2-patterned Si(001) Substrates

Aspect Ratio Trapping is a promising technique for heterointegration of Ge onto Si substrates. By growing Ge in patterned SiO2 trenches, lattice-mismatch dislocations arising from the epitaxial interface can be effectively trapped. However, planarization of these samples is required to enable device fabrication. This paper describes the development and optimization of a chemical mechanical polishing process for these structures. Polishing using diluted Nalco 2360 slurry was investigated, with the addition of NaOCl, NH4OH, or H2O2, for Ge removal rate increase. A slurry mix consisting of Nalco 2360, H2O2, and DI water was shown to have low dishing and low surface metals contamination, and planarized the Ge Aspect Ratio Trapping samples very effectively.

Defect reduction of GaAs/Si epitaxy by aspect ratio trapping

We report on the metallorganic chemical vapor deposition growth of GaAs on patterned Si (001) substrates, which utilizes the aspect ratio trapping method. It was found that when growing GaAs above the SiO2 trenched region, coalescence-induced threading dislocations and stacking faults originated on top of the GaAs/SiO2 interfaces. These defects were found to be indirectly related to the initial defect-trapping process during trenched GaAs growth. Causes of coalescence defect formation and its reduction were experimentally investigated by employing a two-step growth optimization scheme. Improvement of material quality has been characterized by cross-sectional and plan-view transmission electron microscopy and x-ray diffraction.