Aspect Ratio Trapping Research Articles

Simulation design of silicon based quantum well nanolaser based on surface plasmon polariton

We propose a silicon based quantum well nanolaser structure based on surface plasmon polariton (SPP). The InGaAs/InP multi-quantum well in this structure can be obtained by direct epitaxy growth in nanoscale V-grooved trenches on silicon substrate by the high aspect ratio trapping method; and through the deposition of the metal layer and dielectric layer to excite the property of the SPP. The finite element method is used to simulate the electric field distribution of the laser mode and the variation of the mode characteristics, waveguide characteristics and threshold characteristic of the optical communication band with the geometric parameters. The results show that this structure has a better ability to limit the optical field and can realize deep sub-wavelength constraint of the output optical field at a lower threshold level, which is an expected idea of the high-performance and miniaturized silicon-based nanolaser.

Micrometer-scale InP selectively grown on SOI for fully integrated Si-photonics

Practical applications of low-defect III–V materials grown on Si require large areas for patterning metal contacts and enhancing design flexibility. Here, we report selective area growth of bufferless and micrometer-scale InP on commercial (001)-oriented silicon-on-insulators. We obtained in-plane, centimeter-long and micrometer-wide InP single crystal stripes right atop the buried oxide layer through leveraging the lateral aspect ratio trapping (lateral ART) growth method. Using the extended InP grown by “lateral ART,” we inserted InGaAs quantum wells emitting at the telecom bands. Numerical simulation suggests that the micrometer-scale InP can support the fundamental TE mode with an ultra-low metal-induced propagation loss of 3.2 dB/cm when patterned into ridge waveguides and introducing metal contacts at both ends. Our results here represent a leap toward electrically driven III–V lasers seamlessly interfaced with Si-photonics.

(Invited) Advanced Transistors for High Frequency Applications

Downscaling CMOS technology has allowed the integration of high-speed transceivers on silicon chips, but high-power amplifiers rely on III-V technologies to deliver the power and efficiency levels required by modern radios. In this work, we explore two routes to enable the fabrication of compound semiconductor devices on a large-scale manufacturable Si platform. In the first route, we report on Al(Ga,In)N HEMTs, MISHEMTs and MOSFETs integrated on 200 mm Si wafers using Au-free processing in standard Si CMOS tools. In the second route, we demonstrate GaAs/InGaP HBTs grown on a 300 mm Si substrate using Nano-Ridge Engineering (NRE) combined with aspect ratio trapping (ART). We provide insight on the potential of these new technologies for the design of advanced front-end modules, including performance trade-offs, modelling and reliability challenges.

Nano-Ridge Engineering of GaSb for the Integration of InAs/GaSb Heterostructures on 300 mm (001) Si

Nano-ridge engineering (NRE) is a novel heteroepitaxial approach for the monolithic integration of lattice-mismatched III-V devices on Si substrates. It has been successfully applied to GaAs for the realization of nano-ridge (NR) laser diodes and heterojunction bipolar transistors on 300 mm Si wafers. In this report we extend NRE to GaSb for the integration of narrow bandgap heterostructures on Si. GaSb is deposited by selective area growth in narrow oxide trenches fabricated on 300 mm Si substrates to reduce the defect density by aspect ratio trapping. The GaSb growth is continued and the NR shape on top of the oxide pattern is manipulated via NRE to achieve a broad (001) NR surface. The impact of different seed layers (GaAs and InAs) on the threading dislocation and planar defect densities in the GaSb NRs is investigated as a function of trench width by using transmission electron microscopy (TEM) as well as electron channeling contrast imaging (ECCI), which provides significantly better defect statistics in comparison to TEM only. An InAs/GaSb multi-layer heterostructure is added on top of an optimized NR structure. The high crystal quality and low defect density emphasize the potential of this monolithic integration approach for infrared optoelectronic devices on 300 mm Si substrates.

Time-resolved photoluminescence characterization of InGaAs/GaAs nano-ridges monolithically grown on 300 mm Si substrates

The monolithic growth of III–V materials directly on Si substrates provides a promising integration approach for passive and active silicon photonic integrated circuits but still faces great challenges in crystal quality due to misfit defect formation. Nano-ridge engineering is a new approach that enables the integration of III–V based devices on trench-patterned Si substrates with very high crystal quality. Using selective area growth, the III–V material is deposited into narrow trenches to reduce the dislocation defect density by aspect ratio trapping. The growth is continued out of the trench pattern and a box-shaped III–V nano-ridge is engineered by adjusting the growth parameters. A flat (001) GaAs nano-ridge surface enables the epitaxial integration of a common InGaAs/GaAs multi-quantum-well (MQW) structure as an optical gain medium to build a laser diode. In this study, a clear correlation is found between the photoluminescence (PL) lifetime, extracted from time-resolved photoluminescence (TRPL) measurements, with the InGaAs/GaAs nano-ridge size and defect density, which are both predefined by the nano-ridge related pattern trench width. Through the addition of an InGaP passivation layer, a MQW PL lifetime of up to 800 ps and 1000 ps is measured when pumped at 900 nm (only QWs were excited) and 800 nm (QWs + barrier excited), respectively. The addition of a bottom carrier blocking layer further increases this lifetime to ∼2.5ns (pumped at 800 nm), which clearly demonstrates the high crystal quality of the nano-ridge material. These TRPL measurements not only deliver quick and valuable feedback about the III–V material quality but also provide an important understanding for the heterostructure design and carrier confinement of the nano-ridge laser diode.

Bufferless 1.5 µm III-V lasers grown on Si-photonics 220 nm silicon-on-insulator platforms

Efficient III-V lasers directly grown on Si remain the “holy grail” for present Si-photonics research. In particular, a bufferless III-V laser grown on the Si-photonics 220 nm silicon-on-insulator (SOI) platform could seamlessly bridge the active III-V light sources with the passive Si-based photonic devices. Here we report on the direct growth of bufferless 1.5 µm III-V lasers on industry-standard 220 nm SOI platforms using metal organic chemical vapor deposition (MOCVD). Taking advantage of the constituent diffusivity at elevated growth temperatures, we first devised a MOCVD growth scheme for the direct hetero-epitaxy of high-quality III-V alloys on the 220 nm SOI wafers through synergizing the conventional aspect ratio trapping (ART) and the lateral ART methods. In contrast to prevalent epitaxy inside V-grooved pockets, our method features epitaxy inside trapezoidal troughs and thus enables the flexible integration of different III-V compounds on SOIs with different Si device layer thicknesses. Then, using InP as an example, we detailed the growth process and performed extensive study of the crystalline quality of the epitaxial III-V. Finally, we designed and fabricated both pure InP and InP/InGaAs lasers, and we achieved room-temperature lasing in both the 900 nm band and the 1500 nm band under pulsed optical excitation. Direct epitaxy of these in-plane and bufferless 1.5 µm III-V lasers on the 220 nm SOI platform suggests the imminent interfacing with Si-based photonic devices and the subsequent realization of fully integrated Si-based photonic circuits.

Novel adiabatic coupler for III-V nano-ridge laser grown on a Si photonics platform.

While III-V lasers epitaxially grown on silicon have been demonstrated, an efficient approach for coupling them with a silicon photonics platform is still missing. In this paper, we present a novel design of an adiabatic coupler for interfacing nanometer-scale III-V lasers grown on SOI with other silicon photonics components. The starting point is a directional coupler, which achieves 100% coupling efficiency from the III-V lasing mode to the Si waveguide TE-like ground mode. To improve the robustness and manufacturability of the coupler, a linear-tapered adiabatic coupler is designed, which is less sensitive to variations and still reaches a coupling efficiency of around 98%. Nevertheless, it has a relatively large footprint and exhibits some undesired residual coupling to TM-like modes. To improve this, a more advanced adiabatic coupler whose geometry is varied along its propagation length is designed and manages to reach ∼100% coupling and decoupling within a length of 200 μm. The proposed couplers are designed for the particular case of III-V nano-ridge lasers monolithically grown using aspect-ratio-trapping (ART) together with nano-ridge engineering (NRE) but are believed to be compatible with other epitaxial III-V/Si integration platforms recently proposed. In this way, the presented coupler is expected to pave the way to integrating III-V lasers monolithically grown on SOI wafers with other photonics components, one step closer towards a fully functional silicon photonics platform.

Low-Threshold Epitaxially Grown 1.3-μm InAs Quantum Dot Lasers on Patterned (001) Si

A three-fold reduction of threshold current, with a minimum threshold current density of 286 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a maximum operating temperature of 80 °C, and a maximum 3-dB bandwidth of 5.8 GHz was achieved for 1.3- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m InAs quantum dot lasers on patterned, on-axis (001) Si. This was enabled by the reduced threading dislocation density (from 7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> to 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−2</sup> ), and optimized probe design. The patterned Si produced antiphase domain free material in the coalesced GaAs buffer layer with reduced misfit/threading dislocation nucleation, without the use of Ge/GaP buffers or substrate miscut. Utilizing aspect ratio trapping, cyclic thermal annealing, and dislocation filter layers, high-quality III–V on Si devices were grown, demonstrating the compelling advantages of this patterned Si template for a monolithic Si photonics integration platform.

Selective lateral epitaxy of dislocation-free InP on silicon-on-insulator

Efficient on-chip laser sources of Si photonics can be built from direct epitaxy of dislocation-free III–V alloys on industrial-standard (001) Si wafers. Here, we report on selective lateral epitaxy of InP on patterned (001) silicon-on-insulators (SOIs) by metal organic chemical vapor deposition. Based on the conventional “aspect ratio trapping” approach, we created undercut patterns to alter the growth front to the lateral direction. Growth of InP inside the nano-scale SOI trenches results in dislocation-free InP crystals right atop the buried oxide layer. The intimate placement of the InP crystals with the Si device layer points to the development of dislocation-free nano-ridges for integration of efficient III–V light emitters with Si-based photonic components on SOI.

MOCVD grown low dislocation density GaAs-on-V-groove patterned (001) Si for 1.3 μ m quantum dot laser applications

We report the development of gallium arsenide (GaAs) films grown on V-groove patterned (001) silicon (Si) by metalorganic chemical vapor deposition. This technique can provide an advanced virtual substrate platform for photonic integrated circuits on Si. A low defect density of 9.1 × 106 cm−2 was achieved with the aspect ratio trapping capability of the V-grooved Si and dislocation filtering approaches including thermal cycle annealing and dislocation filter layers. The efficiencies of these dislocation reduction methods are quantified by statistical electron channeling contrast imaging characterization. Meanwhile, different sets of dislocation filtering layers are evaluated and optimized. To further demonstrate the suitability of GaAs on the V-grooved Si technique for Si-based photonic devices, especially for the appealing 1.3 μm quantum dot (QD) lasers, a 7-layer indium arsenide QD structure was grown on both GaAs-on-V-grooved Si and native GaAs substrates. The same photoluminescence intensity and full-width at half-maximum values were observed for both structures. The optimization methodology in this work therefore offers a feasible approach to realize high quality III–V materials on Si for large-scale integration.

Defect Characterization of InAs/InGaAs Quantum Dot p-i-n Photodetector Grown on GaAs-on-V-Grooved-Si Substrate

The performance of semiconductor devices on silicon can be severely degraded by the presence of dislocations incurred during heteroepitaxial growth. Here, the physics of the defect mechanisms, characterization of epitaxial structures, and device properties of waveguide photodetectors (PDs) epitaxially grown on (001) Si are presented. A special GaAs-on-V-grooved-Si template was prepared by combining the aspect ratio trapping effects, superlattice cyclic, and strain-balancing layer stacks. A high quality of buffer structure was characterized by atomic force microscopy (AFM) and electron channeling contrast imaging (ECCI) results. An ultralow dark current density of 3.5 × 10–7A/cm2 at 300 K was measured under −1 V. That is 40× smaller than the best reported value of epitaxially grown InAs/GaAs quantum dot photodetector structure on GaP/Si substrate. Low frequency noise spectroscopy was used to characterize the generation and recombination related deep levels. A trap with an activation energy of 0.4 eV was id...

Selective Area Growth of InGaAs/InP Quantum Well Nanowires on SOI Substrate

In recent years, silicon photonic integrated circuits have been extensively studied, which is becoming a promising platform for higher speed interconnect and complex higher functionality with low cost. However, silicon is of indirect bandgap, and thus extremely hard for light emitting, especially at room temperature. By using aspect-ratio trapping (ART) technique, selective area epitaxy of III–V materials on Si shows advantages for monolithic integration of III-Vs on silicon, with defects trapped at the bottom of epitaxial materials. We have directly grown III-V nanowires with an InGaAs/InP quantum well (QW) in the V-grooves on SOI substrates by a MOCVD system. SOI substrates with an oxide layer buried are good at preventing a majority of light leak into the silicon underneath.Therefore a stable optical mode is supposed to be in the III-V nanowires when the scale of cross section down to subwavelength. A low temperature (LT) GaAs was initially deposited at 400 °C as a seeding layer. Then a high temperature (HT) GaAs at 630 °C was performed to fill V-grooves, and used as an intermediary layer for following InP growth, owing to the lattice mismatch of of GaAs to Si (4%) lower than that of InP to Si (8%). So the next performance was 400 °C LT-InP and 650 °C HT-InP growths on the bottom GaAs in trenches, leading to high quality of top InP. The following was the growth of a InGaAs quantum well layer and a InP capping layer. The In/Ga molar ratio of precursors in quantum-well growth was 1.1. We measured the micro photoluminescence (μPL) spectra of the III-V nanowires with the InGaAs/InP quantum well at room temperature. Two large peaks were observed at around 1310 nm and 1550 nm. When the pump power is one tenth of the original, the peak around 1310 nm is greatly reduced, mainly leaving the peak near 1550 nm. The observed μPL spectra are mainly influenced by three factors——the thickness uniformity of the QW, the composition uniformity of the In atoms, and the energy of the pumping source. The InGaAs/InP QW grown by this method is of the "∧" shape, and the thickness of the QW is gradually thickened from the bottom to the top, causing the spectrum to broaden toward long wavelengths, If the InGaAs QW has the same elemental composition everywhere. However, when the InGaAs material is epitaxially grown on a non-planar structure, the In atoms move faster at the high-curvature surface. Therefore, the In composition of the InGaAs material in the top QW is relatively low, and the corresponding bandgap energy is larger. Since the composition of In atoms in the ∧-shaped QW is not a constant, resulting in the bandgap width of the QW is not a constant. When a laser beam penetrates into the QW, the hole electron pairs in the narrow bandgap recombines firstly to emit light of long wavelength. If the number of pump photons is sufficient, it will continue to excite the hole electron pairs in the wide bandgap to recombine, and emit light of short wavelength. Figure 1

Selective Area Growth of InGaAs/InP Quantum Well Nanowires on SOI Substrate

In this paper, we directly grew the InGaAs/InP quantum well nanowires on the v-grooves patterned SOI substrate by metal organic chemical vapor deposition using aspect ratio trapping technique. The surface morphology of the III-V nanowires, the thickness of the quantum wells and the photoluminescence spectra of the InGaAs/InP quantum well nanowires were characterized by scanning electron microscopy, transmission electron microscopy, and micro photoluminescence, respectively. It was found that the thickness inhomogeneity of the quantum well, the composition inhomogeneity of the quantum well and the pump power density irradiated onto the surface of nanowire are the three major factors affecting the micro-photoluminescence spectra.

Understanding and improving the low optical emission of InGaAs quantum wells grown on oxidized patterned (001) silicon substrate

In 0.3 Ga 0.7 As quantum wells (QW) embedded in AlGaAs barriers and grown on oxidized patterned (001) silicon substrates by metalorganic chemical vapor deposition using the aspect ratio trapping method are studied. An appropriate method combining cathodoluminescence and high resolution scanning transmission electron microscopy characterization is performed to spatially correlate the optical and structural properties of the QW. A triple period (TP) ordering along the ⟨111⟩ direction induced by the temperature decrease during the growth to favor indium incorporation and aligned along the oxidized patterns is observed in the QW. Local ordering affects the band gap and contributes to the decrease of the optical emission efficiency. Using thermal annealing, we were able to remove the TP ordering and improve the QW optical emission by two orders of magnitude.

InGaAs/InP quantum wires grown on silicon with adjustable emission wavelength at telecom bands

We report the growth of vertically stacked InGaAs/InP quantum wires on (001) Si substrates with adjustable room-temperature emission at telecom bands. Based on a self-limiting growth mode in selective area metal–organic chemical vapor deposition, crescent-shaped InGaAs quantum wires with variable dimensions are embedded within InP nano-ridges. With extensive transmission electron microscopy studies, the growth transition and morphology change from quantum wires to ridge quantum wells (QWs) have been revealed. As a result, we are able to decouple the quantum wires from ridge QWs and manipulate their dimensions by scaling the growth time. With minimized lateral dimension and their unique positioning, the InGaAs/InP quantum wires are more immune to dislocations and more efficient in radiative processes, as evidenced by their excellent optical quality at telecom-bands. These promising results thus highlight the potential of combining low-dimensional quantum wire structures with the aspect ratio trapping process for integrating III–V nano-light emitters on mainstream (001) Si substrates.

Monolithic integration of InGaAs/InP multiple quantum wells on SOI substrates for photonic devices

A direct epitaxy of III-V nanowires with InGaAs/InP multiple quantum wells on v-shaped trenches patterned silicon on insulator (SOI) substrates was realized by combining the standard semiconductor fabrication process with the aspect ratio trapping growth technique. Silicon thickness as well as the width and gap of each nanowire were carefully designed to accommodate essential optical properties and appropriate growth conditions. The III-V element ingredient, crystalline quality, and surface topography of the grown nanowires were characterized by X-ray diffraction spectroscopy, photoluminescence, and scanning electron microscope. Geometrical details and chemical information of multiple quantum wells were revealed by transmission electron microscopy and energy dispersive spectroscopy. Numerical simulations confirmed that the optical guided mode supported by one single nanowire was able to propagate 50 μm with ∼30% optical loss. This proposed integration scheme opens up an alternative pathway for future photonic integrations of III-V devices on the SOI platform at nanoscale.

Heterointerface study of InAs/GaSb nanoridge heterostructures grown by metal organic chemical vapor deposition on V-grooved Si (0 0 1) substrates

InAs/GaSb nanoridge heterostructures were grown on V-grooved (0 0 1) Si by metal organic chemical vapor deposition. Combining the aspect ratio trapping process and a low temperature GaAs buffer, we demonstrated high quality GaSb nanoridge templates for InAs/GaSb heterostructure growth. Two different interfaces, a transitional GaAsSb and an InSb-like interface, were investigated when growing these heterostructures. A 500 °C growth temperature in conjunction with a GaAsSb interface was determined to produce the optimal interface, properly compensating for the tensile strain accumulated when growing InAs on GaSb. Without the need for a complicated switching sequence, this GaAsSb-like interface utilized at the optimized temperature is the initial step towards InAs/GaSb type II superlattice and other device structures integrated onto Si.

Continuous-wave lasing from InP/InGaAs nanoridges at telecommunication wavelengths

We report continuous-wave lasing from InP/InGaAs nanoridges grown on a patterned (001) Si substrate by aspect ratio trapping. Multi-InGaAs ridge quantum wells inside InP nanoridges are designed as active gain materials for emission in the 1500 nm band. The good crystalline quality and optical property of the InGaAs quantum wells are attested by transmission electron microscopy and microphotoluminescence measurements. After transfer of the InP/InGaAs nanoridges onto a SiO2/Si substrate, amplified Fabry-Perot resonant modes at room temperature and multi-mode lasing behavior in the 1400 nm band under continuous-wave optical pumping at 4.5 K are observed. This result thus marks an important step towards integrating InP/InGaAs nanolasers directly grown on microelectronic standard (001) Si substrates.

Monolithically integrated InAs/InGaAs quantum dot photodetectors on silicon substrates

We report InAs/InGaAs quantum dot (QD) waveguide photodetectors (PD) monolithically grown on silicon substrates. A high-crystalline quality GaAs-on-Si template was achieved by aspect ratio trapping together with the combined effects of cyclic thermal annealing and strain-balancing layer stacks. An ultra-low dark current of 0.8 nA and an internal responsivity of 0.9 A/W were measured in the O band. We also report, to the best of our knowledge, the first characterization of high-speed performance and the first demonstration of the on-chip photodetection for this QD-on-silicon system. The monolithically integrated waveguide PD shares the same platform as the previously demonstrated micro-ring lasers and can thus be integrated with laser sources for power monitors or amplifiers for pre-amplified receivers.

Epitaxial growth of GaSb on V-grooved Si (001) substrates with an ultrathin GaAs stress relaxing layer

We report epitaxial growth of GaSb nano-ridge structures and planar thin films on V-groove patterned Si (001) substrates by leveraging the aspect ratio trapping technique. GaSb was deposited on {111} Si facets of the V-shaped trenches using metal-organic chemical vapor deposition with a 7 nm GaAs growth initiation layer. Transmission electron microscopy analysis reveals the critical role of the GaAs layer in providing a U-shaped surface for subsequent GaSb epitaxy. A network of misfit dislocations was uncovered at the GaSb/GaAs hetero-interface. We studied the evolution of the lattice relaxation as the growth progresses from closely pitched GaSb ridges to coalesced thin films using x-ray diffraction. The omega rocking curve full-width-at-half-maximum of the resultant GaSb thin film is among the lowest values reported by molecular beam epitaxy, substantiating the effectiveness of the defect necking mechanism. These results thus present promising opportunities for the heterogeneous integration of devices based on 6.1 Å family compound semiconductors.