Arsine Ambient Research Articles

Thermal Diffusion of Si Atoms in Delta-Doped n-Type InAlAs Grown by Metal-Organic Vapor-Phase Epitaxy

We studied the thermal diffusion of Si atoms in delta-doped n-type InAlAs grown by metal-organic vapor-phase epitaxy using secondary ion mass spectroscopy (SIMS). In the case of high sheet concentration of around 1×1013 cm-2, significant broadening of the Si profile was observed after postgrowth annealing in arsine ambient at >590°C. In contrast, broadening of the profile was suppressed at the concentration of about 3×1012 cm-2. Diffusivity of Si atom in delta-doped InAlAs was estimated from the SIMS profiles.

Metalorganic vapor-phase epitaxy (MOVPE) growth of InGaAsP multiple-quantum-well distributed feedback lasers on InP corrugated substrate

We describe metalorganic vapor-phase epitaxy (MOVPE) growth of InGaAsP multiple-quantum-well (MQW) distributed feedback (DFB) lasers. The MQWs and optical guide layers were grown directly on a corrugated InP substrate, whose corrugation was preserved by a layer pregrown in a mixed arsine and triethylgallium flow at 350°C. Before the pregrowth, only hydrogen flowed over the corrugated InP substrate. The corrugated InP substrate with the pregrowth layer was heated to 650°C in an arsine ambient, then an InGaAsP waveguide layer and MQW layers were grown. The pregrowth layer was confirmed to be InGaAsP, enabling us to grow a thin InGaAsP waveguide layer to realize small optical confinement inside the MQW active layers. A fabricated laser diode operating at 1.62 μm showed a threshold current of 10.2 mA and an external quantum efficiency of 0.28 mW/mA at an ambient temperature of 25°C. A side longitudinal mode suppression ratio of 40 dB at an optical output power of 10 mW was obtained, in the range from −20 to 85°C.

Recrystallization of Amorphous Layer in Ion Implanted GaAs - Transmission Electron Microscopy Studies

2 MeV arsenic or gallium ions were used to produce nonstoichiometric buried amorphous layers in gallium arsenide. The mechanism of thermally induced regrowth of tlese layers was investigated using transmission electron microscopy. Low-temperature annealing resulted in nucleation of high den- sities of stacking faults. This was associated with the local nonstoichiometry of the amorphous layers. After annealing at high temperatures, in arsenic as well as in gaflium implanted samples, two layers of voids, formed in result of vacancies clustering, were found in areas adjacent to the initial location of the amorphous-crystalline interfaces. A qualitative model of the formation of such layers was proposed. PACS numbers: 61.80.Jh, 6l.72.Cc, 61.72.Ff Ion implantation is a commonly used technique for electronic device process- ing. Therefore, in the past decades there have been numerous studies concerning the damage produced b y ion implantation into semiconduction and its thermal recovery. Despite all these investigations there are still many unsolved problems. In this paper, two issues will be discussed. The first concerns the influence of local nonstoichiometry of an amorphous layer on its regrowth (1, 2). The second is the mechanism of formation of layers of voids, during ligh-temperature annealing. Semi-insulating (100) gallium arsenide (GaAs) wafers were implanted with 2 MeV arsenic (As) or gallium (Ga) ions at doses of 1 x 10 16 cm -2 and 5 x 10 15 cm -2 , respectively. For both the materials cross-sectional transmission electron microscopy (TEM) showed that applied doses were high enough to pro- duce buried amorphous layers. After implantation some pieces of the materials were annealed for 20 minutes in selected temperatures between 300°C and 800°C. In order to prevent arsenic outdiffusion from the surface annealing was performed under arsine ambient in MOCVD reactor. Cross-sectional TEM samples were pre- pared afterwards.

Ultrafast carrier trapping in high energy ion implanted gallium arsenide

Time resolved photoluminescence and electrical measurements were made on MeV As, Ga, Si, and O ion implanted GaAs to doses in the range of 1×1014–5×1016 cm−2 and subsequently annealed at 600 °C for 20 min under arsine ambient. Carrier trapping times were found to decrease with increase in implantation dose for all species studied and can be shorter than 1 ps. Sheet resistance values were found to be independent of implantation dose and were of the order of 108 Ω/⧠ for As, Ga, and O implantation and ∼2×102 Ω/⧠ for the Si case due to its electrical activation. Conductivity activation energies of 0.67–0.69 eV were observed for As, Ga, and O ion implanted and annealed GaAs, which are close to the reported activation energy for annealed low-temperature GaAs (0.65 eV).

Effect of Annealing Method on Vacancy-Type Defects in Si-Implanted GaAs Studied by a Slow Positron Beam

The effect of annealing encapsulants on the activation of Si implanted into GaAs was studied by slow positron beam annihilation. For encapsulants, two kinds of silicon nitrides and silicon dioxide were used and capless annealing under arsine ambient was performed for reference purposes. From the measurements of the Doppler-broadened profiles of the positron annihilation as a function of the incident positron energy, gallium vacancy concentrations were estimated. It was found that silicon dioxide cap annealing includes a high concentration of gallium vacancies, which is approximately 2.5 times larger than that for silicon nitride annealing and four times that for capless annealing. With the electrical measurement, the out-diffusion of Ga into the cap insulator film was found to have no enhancing effect on electrical activation.

Pyrolysis of trimethylgallium on GaAs(100) surfaces

We have used a combination of pulsed molecular beam and time-resolved mass spectrometry to study the kinetics of the pyrolysis of trimethylgallium on GaAs(100) surfaces. We found that CH3 is the major reaction product. Two CH3 desorption channels were observed, with activation energies 37.9±1.6 and 45.0±1.4 kcal/mole. An arsine ambient significantly accelerates the CH3 desorption, but no CH4 was observed. A model for the reaction of trimethylgallium on the GaAs(100) surface is proposed.

Mg implant activation and diffusion in GaAs during rapid thermal annealing in arsine ambient

Rapid thermal annealing of GaAs in an arsine ambient has been investigated. Uncapped 2-in. GaAs wafers were annealed in an arsine-N2 gas mixture up to annealing temperatures of 1100 °C and annealing times of 10 s. No surface decomposition occurred at an arsine partial pressure of 12.5 Torr. This capless annealing technique was employed to the activation of shallow Mg implants in GaAs. The sheet resistance of the annealed layers as a function of the annealing temperature reveals a minimum at approximately 930 °C. At higher temperatures diffusion of Mg becomes significant. A part of the Mg accumulates at the GaAs surface and diffuses out. The Mg loss due to outdiffusion can be reduced using Si3 N4 cap layers. The internal diffusion of Mg at high temperatures depends on the arsenic pressure during the annealing.

Low-Energy Implantation of Si and Sn into GaAs

ABSTRACT(100) GaAs was implanted with 29Si+ at energies of 10keV or 20keV and 119Sn+ at an energy of 60keV. The doses used for the Si+ implants were from 1 × 1013 crrr2 to 1 × 1016 cm-2, whereas the Sn+ doses ranged from 1.5×1012 cm-2 to 1.5×1015 cm-2. Implanted samples were rapidly thermal annealed (RTA) in either an argon or arsine ambient at 950°C or 900°C for 12 seconds. Transmission electron microscopy (TEM) results indicate that the annealing ambient has a dramatic effect on the defect annealing kinetics for 10keV implants but not the 20keV Si+ implants. For the 10keV implants reducing arsenic loss via use of an arsine ambient or a Si3N4 cap results in a dramatic decrease in the dislocation loop density. The defect morphology is not related to the as implanted morphology (amorphous or crystalline) but is related to the species. Hall effect measurements revealed an increase in the mobility by a factor of 1.5 times for high dose Si+ and Sn+ implanted samples when RTA was carried out in an arsine instead of an argon ambient. This is despite little or no change in the extended defect morphology or carrier concentration, indicating that the point defect concentration influences the mobility.

Shallow Doping of Gallium Arsenide by Recoil Implantation

AbstractSi atoms were recoil-implanted into GaAs by bombarding neutral (As+) or dopant (Si+) ions through a thin Si cap. The bombarded samples were subsequently rapid thermally or furnace annealed at 815–1000°C in Ar or arsine ambient. The presence of the recoiled Si in GaAs and resulting ni-doping was confirmed by secondary ion mass spectrometry and Hall measurements. It was found that sheet resistances of < 150 Ω/‪ can be achieved by this method. Capless furnace annealing in arsine ambient generally yielded better electrical results (especially for shallow implants, i.e., < 100 nm deep) compared to those obtained by RTA in an inert ambient with a Si cap. In the latter case, electrical activation deteriorated above 900°C due to high As loss and the deterioration was pronounced for shallow implants. Significant Si redistribution occurred during arsine annealing whenever the Si concentration (from recoil or direct implant) in GaAs exceeded 1×1019cm3 and the annealing temperature was > 850°C. Our present electrical data show that the recoil implant method is a viable alternative to direct shallow implant for n+ doping of GaAs.

Influence of annealing and substrate orientation on metalorganic chemical vapor deposition GaAs on silicon heteroepitaxy

GaAs layers grown on misoriented silicon substrates are examined for defect reduction as a function of thermal annealing and degree of misorientation. These GaAs layers (3–4 μm) are grown by a two-step metalorganic chemical vapor deposition process on Si substrates misoriented 1°, 1.5°, 2°, 3°, 4°, and 6° from (100) toward [011]. Annealing takes place in an open tube furnace under an arsine ambient at 850 °C for one or two 30-min cycles. Double-crystal x-ray rocking measurements and plan-view and cross-section transmission electron microscopy are used to evaluate the resulting crystal quality. Prior to annealing, all cases exhibit approximately equal defect densities with the average size of the microtwins being a function of misorientation. There also exists an anisotropy in the microtwin variant distribution in the layers. After annealing, however, the defect density is found to be dependent on the misorientation. The 1° and 2° layers, which have smaller microtwins, exhibit a greater reduction in defect density after thermal cycling than the 4° and 6° layers. The annealed 4° and 6° layers instead exhibit larger microtwins on average than the as-grown layers. These data indicate that smaller microtwins are more likely to be annihilated through thermal cycling. In addition to the change in the microtwin structures, thermal cycling produces elongated dislocations in the 1° and 2° layers and dislocation tangles associated with the remaining microtwins in the 4° and 6° layers.

Arsine Ambient Rapid Thermal Annealing

ABSTRACTWe have constructed a multiple wafer arsine ambient rapid thermal anneal (RTA) system and have applied it to the fabrication of high-performance refractory-gate self-aligned GaAs MESFETs. This has allowed us to take advantage of some of the features of rapid thermal annealing for these devices (reduced dopant movement and gate-channel interaction) without the difficulties of capped RTA (decapping problems, cap thermal mismatch stress driven dopant movement and gate-channel interaction) or the uncertain As loss characteristics of uncapped or proximity RTA. The anneal system uses a cylindrical furnace with a graphite boat heated by tungsten lamps with a 60 KW maximum power input. This allows heating rates in excess of 100°C/sec for up to four, two-inch wafers per run with a controlled arsine ambient of 0–20 Torr in an inert gas carrier. Closed loop temperature control is accomplished using a 5 μm wavelength optical pyrometer. The system has been designed to collect the As cracked from AsH, in a downstream trap and essentially no As is deposited in the wafer load area.Using arsine ambient RTA to anneal 15 KV 20Si+ self-aligning implants for GaAs MESFETs with MOCVD grown channels (30 nm, 1.7 × 1018/cm3), we have been able to fabricate enhancementmode self-aligned MESFETs with gm/gd > 20 and extrinsic k-factor as large as 765 mS/V-mm for 0.15 μm gate length.

Prevention of thermal surface damage in GaAs by encapsulated annealing in an arsine ambient

This paper shows that both capped and capless techniques commonly used in the high temperature annealing of GaAs can cause thermal surface damage characterized by a decrease in the net carrier concentration in a region within a few micrometers of the surface. This thermal surface damage can be prevented by a technique of encapsulated annealing in an arsine ambient.

Annealing of zinc-implanted GaAs

A study of ion-implanted zinc in GaAs has been made using three annealing techniques: e-beam, graphite strip heating, and furnace annealing in an arsine ambient. The highest hole concentrations, 7–8×1019 cm−3, were obtained using electron-beam annealing. Graphite strip heating and electron-beam annealing were able to electrically activate 100% of the implanted dose. The effect of strain on the activation of the zinc has been demonstrated by comparing chemical-vapor-deposited Si3N4 with reactively evaporated AlN encapsulants.

Annealing of selenium-implanted GaAs

The electrical and structural properties of 1×1014 Se+ cm−2, 100–400 kV and 5×1012 Se++ cm−2, 350-kV implants into (100) semi-insulating GaAs have been studied. Peak carrier concentrations of 5×1018 cm−3 have been measured and mobilities >4000 cm2 V−1 s−1 obtained for low-dose implants (n=1–2×1017 cm−3) by annealing samples on a graphite strip heater. Si3N4 and AlN have been used as encapsulants. Comparisons are made with capless annealing in an arsine ambient.

Enhanced protection of GaAs against thermal surface degradation by encapsulated annealing in an arsine ambient

This letter reports a technique of encapsulated annealing in an arsine ambient which is shown to provide better surface protection for GaAs against thermal degradation than either encapsulation alone or capless annealing in arsine.