Array Low-density Parity-check Research Articles

Failure Analysis of the Interval-Passing Algorithm for Compressed Sensing

In this work, we perform a complete failure analysis of the interval-passing algorithm (IPA) for compressed sensing. The IPA is an efficient iterative algorithm for reconstructing a $k$ -sparse nonnegative $n$ -dimensional real signal ${x}$ from a small number of linear measurements ${y}$ . In particular, we show that the IPA fails to recover ${x}$ from ${y}$ if and only if it fails to recover a corresponding binary vector of the same support, and also that only positions of nonzero values in the measurement matrix are of importance to the success of recovery. Based on this observation, we introduce termatiko sets and show that the IPA fails to fully recover ${x}$ if and only if the support of ${x}$ contains a nonempty termatiko set, thus giving a complete (graph-theoretic) description of the failing sets of the IPA. Two heuristics to locate small-size termatiko sets are presented. For binary column-regular measurement matrices with no 4-cycles, we provide a lower bound on the termatiko distance , defined as the smallest size of a nonempty termatiko set. For measurement matrices constructed from the parity-check matrices of array low-density parity-check codes, upper bounds on the termatiko distance equal to half the best known upper bound on the minimum distance are provided for column-weight at most 7, while for column-weight 3, the exact termatiko distance and its corresponding multiplicity are provided. Next, we show that adding redundant rows to the measurement matrix does not create new termatiko sets, but rather potentially removes termatiko sets and thus improves performance. An algorithm is provided to efficiently search for such redundant rows. Finally, we present numerical results for different specific measurement matrices and also for protograph-based ensembles of measurement matrices, as well as simulation results of IPA performance, showing the influence of small-size termatiko sets.

Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes

The error floor phenomenon, associated with iterative decoders, is one of the most significant limitations to the applications of low-density parity-check (LDPC) codes. A variety of techniques from code design to decoder implementation have been proposed to address the error floor problem, among which post-processors have shown to be both effective and implementation-friendly. In this paper, we take the inspiration from simulated annealing to generalize the post-processor design using three methods: quenching, extended heating, and focused heating, each of which targets a different error structure. The resulting post-processor is demonstrated to lower the error floors by two orders of magnitude for two structured code examples, a (2209, 1978) array LDPC code and a (1944, 1620) LDPC code used by the IEEE 802.11n standard. The post-processor can be integrated with a belief-propagation decoder with minimal overhead. The post-processor design is equally applicable to other structured LDPC codes.

Dispersed Array LDPC Codes and Decoder Architecture for NAND Flash Memory

Quasi-cyclic (QC) low-density parity-check (LDPC) codes have become popular in NAND flash memories, owing to their excellent error correction performance and hardware-friendly structures. However, the large scale of barrel shifters result in prohibitive routing complexity. Array LDPC code is a kind of highly structured QC-LDPC code, which provides a good balance of performance, complexity, and throughput. In this brief, a construction method of dispersed array LDPC (DA-LDPC) codes based on an array square is proposed. DA-LDPC codes not only benefit from the array property but also a hybrid and efficient storage architecture due to their stair-like structure. For NAND flash applications, the code construction and decoder architecture of a (18300, 16470) DA-LDPC code is illustrated in this brief, where a two-level decision of LDPC decoding strategy is employed. The numerical results based on an FPGA emulation platform have shown that the error floor of the (18300, 16470) DA-LDPC code is under 10−11 in term of bit error rate (BER). Thanks to the well-structured DA-LDPC codes, we can conveniently apply a column-based shuffle decoding (CBSD) algorithm for ease of implementation. The corresponding ASIC implementation results have proved that the decoder architecture of DA-LDPC codes can achieve higher normalized-throughput-gate-count-ratio (NTGR) compared to state-of-art works.

On the Stopping Distance of SA-LDPC Codes by Transversal Designs

In this paper, we analyze the size of the smallest stopping set (called the stopping distance) for the parity-check matrix of a superposed array low-density parity-check (SA-LDPC) code for column weights 3 and 4 by using the transversal design (TD) concept. An SA-LDPC code is obtained as the result of an n -fold recursive product operation (a superposition method) on the parity-check matrix of an array low-density parity-check (array LDPC) code, H n ( m,q ), where n ≥ 2 and m and q are column and row weights, respectively. We provide the lower and upper bounds for the stopping distance of these codes. Our simulation result shows that the SA-LDPC codes can compete with the TD-LDPC codes, random LDPC codes, and lattice LDPC codes of comparable rates and lengths and can improve the error floor region of the bit error rate curve.

Efficient coding techniques algorithm for cluster-heads communication in wireless sensor networks

Random network coding (RNC) for Error Correction have been the subject of intense research lately. However, in wireless sensor networks (WSNs) the correlation between the received symbols, from the same cluster head (CH), provoke the column correlation on the generator matrix of array Low-Density Parity-Check (LDPC) codes, whereby many columns of this matrix do not offer any additional information, thus the most important properties are lost despite the fact that the generator matrices are more easily dispersed. In this paper, the authors describe each step of the problem-solving algorithm employing efficient coding techniques focusing on improvement planning at Bit-error rsate (BER) vs signal-to-noise ratio (SNR) curves, in dense WSN, between CHs and the base station (BS) node. They use efficient coding techniques approach based on RNC and LDPC codes using the Time Division Multiple Access (TDMA) method. They generalize the notion of RNC-LDPC, study their properties and formulate the main steps of the proposed algorithm reconstruction method. The simulation results demonstrate that this approach is more effective in improving the BER using the proposed algorithm. Moreover, subsequently ameliorate the technical properties offered by this codification type.

Compressive Sensing Measurement Matrix Generator Based on Improved SC-Array LDPC Code

We construct and implement a compressive sensing measurement matrix based on improved size-compatible (ISC)-array low-density parity-check (LDPC) code. First, we propose an improved measurement matrix from the array LDPC code matrix. The proposed measurement matrix retains suitable quasi-cyclic structures and supports arbitrary code lengths. It also achieves a high perfect recovery percentage compared with a Gaussian random matrix of the same size. Second, we propose a hardware scheme using cycle shift registers to design the compressive sensing measurement matrix generator. This provides simple circuit architecture during the generation of the measurement matrix. According to simulation verifications, the measurement matrix construction method is effective and entails fewer shift registers and a lower area overhead by using a simplified hardware implementation scheme. The compressive sensing measurement matrix generator can generate all of the required elements in the ISC-array LDPC code matrix with an acceptable hardware overhead. Therefore, it can be widely applied to large-scale sparse signal compressive sensing.

More on the Minimum Distance of Array LDPC Codes

Array low-density parity-check (LDPC) codes are a special class of quasi-cyclic LDPC codes constructed from a pair of integers (m, q), where q is an odd prime, and m ≤ q. In this paper, an improved upper bound on the minimum distance of this class of codes is given.

On the Minimum/Stopping Distance of Array Low-Density Parity-Check Codes

In this work, we study the minimum/stopping distance of array low-density parity-check (LDPC) codes. An array LDPC code is a quasi-cyclic LDPC code specified by two integers q and m, where q is an odd prime and m <= q. In the literature, the minimum/stopping distance of these codes (denoted by d(q,m) and h(q,m), respectively) has been thoroughly studied for m <= 5. Both exact results, for small values of q and m, and general (i.e., independent of q) bounds have been established. For m=6, the best known minimum distance upper bound, derived by Mittelholzer (IEEE Int. Symp. Inf. Theory, Jun./Jul. 2002), is d(q,6) <= 32. In this work, we derive an improved upper bound of d(q,6) <= 20 and a new upper bound d(q,7) <= 24 by using the concept of a template support matrix of a codeword/stopping set. The bounds are tight with high probability in the sense that we have not been able to find codewords of strictly lower weight for several values of q using a minimum distance probabilistic algorithm. Finally, we provide new specific minimum/stopping distance results for m <= 7 and low-to-moderate values of q <= 79.

Generalised array low‐density parity‐check codes

In this study, using Group Permutation Low-Density Parity-Check (GP-LDPC) codes, the authors generalise the concept of array Low-Density Parity-Check (LDPC) codes from fields of prime order to those of prime power order. In fact, they consider the additive group of the finite field GF( q ), q a prime power, as the underlying group for the GP-LDPC code construction and since when q is a prime, the author's code construction method coincides with that of quasi-cyclic array LDPC codes, they call their codes, generalised array LDPC (GA-LDPC) codes. First, they prove that, like array LDPC codes, GA-LDPC codes are quasi-cyclic codes. Then, they analyse the girth of GA-LDPC codes in a way similar to that for array LDPC codes and introduce some shortened GA-LDPC codes with girths 8, 10 and 12. For many values of g , J and L , the lengths of ( J , L )-regular shortened GA-LDPC codes of girth g and rate at least 1 - J / L , constructed in this study, are smaller than the lengths of ( J , L )-regular LDPC codes of girth g and rate at least 1 - J / L , constructed in the literature. Also, simulation results show that GA-LDPC codes perform well with the iterative message-passing decoding.

Array Convolutional Low-Density Parity-Check Codes

This paper presents a design technique for obtaining regular time-invariant low-density parity-check convolutional (RTI-LDPCC) codes with low complexity and good performance. We start from previous approaches which unwrap a low-density parity-check (LDPC) block code into an RTI-LDPCC code, and we obtain a new method to design RTI-LDPCC codes with better performance and shorter constraint length. Differently from previous techniques, we start the design from an array LDPC block code. We show that, for codes with high rate, a performance gain and a reduction in the constraint length are achieved with respect to previous proposals. Additionally, an increase in the minimum distance is observed.

Low-complexity girth-8 high-rate moderate length QC LDPC codes

A low-complexity method for constructing a large class of high-rate girth-8 quasi-cyclic low-density parity-check (LDPC) codes with moderate length 1000 < n < 10 000 is presented. This method is based on combining configurations with incidence matrices composed of cyclic permutation matrices and Tanner graph girth at least 8. Shortened lattice codes of length n < 380 and girth 8 are employed as component codes. From the performance perspective, the resulting codes are comparable to their counterparts such as random-like and shortened array LDPC codes.