Dispersed Array LDPC Codes and Decoder Architecture for NAND Flash Memory

Abstract

Quasi-cyclic (QC) low-density parity-check (LDPC) codes have become popular in NAND flash memories, owing to their excellent error correction performance and hardware-friendly structures. However, the large scale of barrel shifters result in prohibitive routing complexity. Array LDPC code is a kind of highly structured QC-LDPC code, which provides a good balance of performance, complexity, and throughput. In this brief, a construction method of dispersed array LDPC (DA-LDPC) codes based on an array square is proposed. DA-LDPC codes not only benefit from the array property but also a hybrid and efficient storage architecture due to their stair-like structure. For NAND flash applications, the code construction and decoder architecture of a (18300, 16470) DA-LDPC code is illustrated in this brief, where a two-level decision of LDPC decoding strategy is employed. The numerical results based on an FPGA emulation platform have shown that the error floor of the (18300, 16470) DA-LDPC code is under 10−11 in term of bit error rate (BER). Thanks to the well-structured DA-LDPC codes, we can conveniently apply a column-based shuffle decoding (CBSD) algorithm for ease of implementation. The corresponding ASIC implementation results have proved that the decoder architecture of DA-LDPC codes can achieve higher normalized-throughput-gate-count-ratio (NTGR) compared to state-of-art works.