Arithmetic Logic Research Articles

Efficient mapping and acceleration of AES on custom multi‐core architectures

AbstractMulti‐core processors can deliver significant performance benefits for multi‐threaded software by adding processing power with minimal latency, given the proximity of the processors. Cryptographic applications are inherently complex and involve large computations. Most cryptographic operations can be translated into logical operations, shift operations, and table look‐ups. In this paper we design a novel processor (called mu‐core) with a reconfigurable Arithmetic Logic Unit, and design custom two‐dimensional multi‐core architectures on top of it to accelerate cryptographic kernels. We propose an efficient mapping of instructions from the multi‐core grid to the individual processor cores and illustrate the performance of AES‐128E algorithm over custom‐sized grids. The model was developed using Simulink and the performance analysis suggests a positive trend towards development of large multi‐core (or multi‐ µ‐core) architectures to achieve high throughputs in cryptographic operations. Copyright © 2010 John Wiley & Sons, Ltd.

Threshold Voltage Variations Make Full Adders Reliabilities Similar

Addition is the most widely used arithmetic operation in digital applications. The reliability of full adder (FA) cells is crucial as they affect arithmetic logic and floating-point units, as well as cache/memory address calculations. This letter studies the reliability of five different FA designs. The analysis starts from the device level by estimating the effects threshold voltage variations will have on the reliability of scaled CMOS transistors. These estimations will then be used to calculate the reliability of the sum and carry_out signals. This letter will also briefly explore the effects of increasing the reliability of devices and of using gate-level redundancy schemes on the reliability of FAs.

Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors

Energy reduction of functional units (FUs) is a very important concern for high-end superscalar processors, not only because FUs consume a significant portion of processor energy, but also because they are one of the most important hotspots in the processor. In addition, the high sensitivity of leakage on temperature and process variation result in very high variation in the FU power consumption in different processor dies. Such high process variation reduces the parametric yield of processors. Consequently, reducing the FU power consumption and its variation is an important problem. However, existing FU power reduction techniques assumes all the FUs are similar, and do not consider the sensitivity of leakage on temperature. Consequently, they are not very effective in reducing the variation of FU power consumption. The advent of extremely small, yet accurate leakage sensors allow us to develop leakage-aware microarchitectural techniques to reduce both the power consumption and its variation among processor dies. Our leakage-aware operation-to-FU binding mechanism (LAOFBM) and leakage-aware power gating (LA-PG) mechanisms reduce the mean and standard deviation of the total arithmetic logic unit (ALU) power consumption of the ALPHA 21364 by 34% and 59%, respectively. At the processor level, this translates to a 13% reduction in the total processor energy consumption, with a 24°C reduction in the maximum ALU temperature.

Unconventional Computing — Reversible Signed Digit Adders for Future Nanocomputing Devices

Abstract Unconventional Computing (UC) denotes new and alternative methods and technologies for computer technologies, e. g., nanocomputing or DNA computing. This paper investigates the importance of UC for the Grand Challenges of Computer Engineering. At the moment nanocomputing appears to be the most promising UC discipline. As example for an UC method the use of redundant arithmetic and reversible logic for nanocomputing is presented.

A scheme of developing frequency encoded tristate-optical logic operations using semiconductor optical amplifier

The ever increasing demand for very fast and agile optical networks requires very fast execution of different optical and logical operations as well as large information handling capacities at the same time. In conventional binary logic based operations the information is represented by two distinct states only (0 and 1 state). It limits the large information handling capacity and speed of different arithmetic and optical logic operations. Tristate based logic operations can be accommodated with optics successfully in data processing, as this type of operation can enhance the speed of operation as well as increase the information handling capacity. Here in this communication the author proposes a new method to implement all-optical different logic gates with tristate logic using the frequency-encoding principle. The frequency encoding/decoding based optical communication has distinctly great advantages because the frequency is the fundamental character of an optical signal and it preserves its identity throughout the communication. The principle of the rotation of the state of polarization of a probe beam through semiconductor optical amplifier (SOA), frequency routing property of an optical add/drop multiplexer (AD) and high frequency conversion property of reflecting semiconductor optical amplifiers (RSOA) have been exploited here to implement the desired AND, OR, NAND and NOR logic operations with tristate logic.

Design and verification of an ALU‐based universal FIR filter

PurposeTraditionally, each time a new design for a finite impulse response (FIR) filter is required, a new algorithm has to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. The purpose of this paper is to propose an arithmetic logic unit (ALU)‐based universal FIR filter suitable for realization in field programmable gate arrays (FPGA), where various FIR filters can be implemented just by programming instructions in the ROM with identical hardware architecture.Design/methodology/approachRather than multiplier‐accumulator‐based architecture for conventional FIR, the proposed ALU architecture implements the FIR functions by using accumulators and shift‐registers controlled by the instructions of ROM. Furthermore, time division multiplexing access (TDMA) technique is employed to reduce the chip size. In addition, the proposed FIR architecture is verified in a SOC hardware and/or software co‐emulation system.FindingsAn ALU‐based universal FIR filter suitable for realization in FPGA is designed and verified in a SOC hardware/software co‐emulation system with example of a 64‐tap FIR filter design.Originality/valueA software‐based design method as well as TDMA scheme for the ALU‐based FIR filter are introduced, making FIR filter architecture universal, programmable, and consuming less FPGA resources.

Implementation of an SDR system using graphics processing unit

This article presents a novel procedure of implementing software defined radio modem using a graphics processing unit instead of conventional digital signal processors and/or field programmable gate arrays. Considering that modern GPU is suitable for parallel computing due to its numerous powerful arithmetic logic units, we suggest a proper architecture of hardware and software platform for the SDR modem to be implemented on GPU. Then, we show a design example of mobile WiMAX terminal implemented on the proposed GPU platform. In our experimental tests, we observed that the GPU-driven modem is nearly 90 times faster than the conventional 8-way Very Long Instruction Word architectured DSP-driven modem for the application of Viterbi decoder implementation of mobile WiMAX terminal.

On Translating Frege's Die Grundlagen der Arithmetik

In this essay, I critically discuss Dale Jacquette's new English translation of Frege's work Die Grundlagen der Arithmetik as well as his Introduction and Critical Commentary (Frege, G. 2007. The Foundations of Arithmetic. A Logical-Mathematical Investigation into the Concept of Number. Translated with an Introduction and Critical Commentary by Dale Jacquette. New York: Longman. xxxii + 112 pp.). I begin with a short assessment of Frege's book. In sections 2 and 3, I examine several claims that Jacquette makes in his Introduction and Critical Commentary and put matters in the right perspective. In sections 4–7, I analyse errors and shortcomings in Jacquette's (and Austin's) translation(s) and show how they can be avoided. In this context, I consider several issues of interest for Frege's logic and philosophy of arithmetic. I conclude with general remarks.

New approach FPGA-based implementation of discontinuous SVPWM}

The discontinuous space vector pulse-width modulation (DSVPWM) is a well-known technique offering lower switching losses than continuous SVPWM. At the same, average switching frequency, or a switching frequency 1.5 times higher than utilized in continuous SVPWM, the discontinuous SVPWM results in lower current harmonic distortions than that obtained in continuous SVPWM at high modulation indices. This paper is concerned with the design and realization of new FPGA approach based a 5-segment discontinuous SVPWM operated at 40 kHz switching frequency. It will be shown that the implementation of the discontinuous SVPWM utilized in FPGA, to execute some complex tasks, is simplified through this new straightforward approach. For example, the judging of sectors, the computation of on-duration or firing pulses to control the switching of power switching devices can be executed much simpler with the proposed arithmetic logics or digital calculation in FPGA. In this way, the sampling frequency and hence switching frequency be increased. The SVPWM scheme has been implemented successfully based on APEX20KE Altera FPGA considering hardware resource saving. The validity of the proposed scheme has been tested experimentally to drive a 1.5 kW induction machine with low current harmonic distortions.

A survey of multicore processors

General-purpose multicore processors are being accepted in all segments of the industry, including signal processing and embedded space, as the need for more performance and general-purpose programmability has grown. Parallel processing increases performance by adding more parallel resources while maintaining manageable power characteristics. The implementations of multicore processors are numerous and diverse. Designs range from conventional multiprocessor machines to designs that consist of a "sea" of programmable arithmetic logic units (ALUs). In this article, we cover some of the attributes common to all multicore processor implementations and illustrate these attributes with current and future commercial multicore designs. The characteristics we focus on are application domain, power/performance, processing elements, memory system, and accelerators/integrated peripherals.

Study on the Logical Ideas in Chinese Ancient Mathematics from “Liu Hui’s Commentary of the Chiu Chang Suan Shu” (Research of the Relations between Calculation and Proof, Arithmetic and Logic)

“Liu Hui’s Commentary of the Chiu Chang Suan Shu” is the best commentary for the most important basic book in Chinese ancient mathematics, the Chiu Chang Suan Shu, and it contains large numbers of logical reasoning and logical ideas. Abundant logical ideas and logical contents in Chinese ancient mathematics were contained in Liu Hui’s Commentary. Based on analyzing the items in Liu Hui’s Commentary and relative ancient literatures, abundant logic contents in the Commentary and the logical contents in ancient mathematics were demonstrated from three angles including concept, logical method and symbolic logic in the article. The relations between calculation and proof, arithmetic and logic in ancient mathematics were also expounded in the article, and the conclusions showed that there was proof logic or arithmetic logic existing in the ancient times of China.

PARALLELIZATION OF REVERSIBLE RIPPLE-CARRY ADDERS

The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of garbage. Here, we present a novel parallelization scheme wherein m parallel k-bit reversible ripple-carry adders are combined to form a reversible mk-bit ripple-block carry adder with logic depth [Formula: see text] for a minimal logic depth [Formula: see text], thus improving on the mk-bit ripple-carry adder logic depth [Formula: see text]. The underlying mechanisms of the parallelization scheme are formally proven correct. We also show designs for garbage-less reversible comparison circuits. We compare the circuit costs of the resulting ripple-block carry adder with known optimized reversible ripple-carry adders in measures of circuit delay, width, gate, transistor count, and relative power efficiency, and find that the parallelized adder offers significant speedups at realistic word sizes with modest parallelization overhead.

Fabrication Technique of Single Flux Quantum ALU by Using Nb Trilayer

Nb trilayer process has been serving as the most stable fabrication process of the Josephson junction integrated circuits for more than two decades. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipment. In this work, we took an advantage of those advanced fabrication equipments in developing a superconducting arithmetic logic unit (ALU) by using Nb trilayers. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for SiO2 depositions. Various dry etching techniques were used to define Josephson junction areas and various patterns of metallic and insulating layers. Our Nb films were stress-free and had the Tc's above 9 K. To enhance the step coverage of Nb films we used reverse bias DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens gigahertz clock frequency. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at 5 GHz clock frequency.

A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regularnanowire network with hexagonal topology

A two-bit arithmetic logic unit (ALU) was successfully fabricated on a GaAs-based regularnanowire network with hexagonal topology. This fundamental building block of centralprocessing units can be implemented on a regular nanowire network structure with simplecircuit architecture based on graphical representation of logic functions using a binarydecision diagram and topology control of the graph. The four-instruction ALU wasdesigned by integrating subgraphs representing each instruction, and the circuitry wasimplemented by transferring the logical graph structure to a GaAs-based nanowirenetwork formed by electron beam lithography and wet chemical etching. A pathswitching function was implemented in nodes by Schottky wrap gate control ofnanowires. The fabricated circuit integrating 32 node devices exhibits the correctoutput waveforms at room temperature allowing for threshold voltage variation.

Design of highly efficient elliptic curve crypto-processor with two multiplications over GF(2 163)

In this article, a parallel hardware processor is presented to compute elliptic curve scalar multiplication in polynomial basis representation. The processor is applicable to the operations of scalar multiplication by using a modular arithmetic logic unit (MALU). The MALU consists of two multiplications, one addition, and one squaring. The two multiplications and the addition or squaring can be computed in parallel. The whole computations of scalar multiplication over GF(2 163) can be performed in 3 064 cycles. The simulation results based on Xilinx Virtex2 XC2V6000 FPGAs show that the proposed design can compute random GF(2 163) elliptic curve scalar multiplication operations in 31.17 μs, and the resource occupies 3 994 registers and 15 527 LUTs, which indicates that the crypto-processor is suitable for high-performance application.

High-performance hardware architecture of elliptic curve cryptography processor over GF(2163)

We propose a novel high-performance hardware architecture of processor for elliptic curve scalar multiplication based on the Lopez-Dahab algorithm over GF(2163) in polynomial basis representation. The processor can do all the operations using an efficient modular arithmetic logic unit, which includes an addition unit, a square and a carefully designed multiplication unit. In the proposed architecture, multiplication, addition, and square can be performed in parallel by the decomposition of computation. The point addition and point doubling iteration operations can be performed in six multiplications by optimization and solution of data dependency. The implementation results based on Xilinx VirtexII XC2V6000 FPGA show that the proposed design can do random elliptic curve scalar multiplication GF(2163) in 34.11 μs, occupying 2821 registers and 13 376 LUTs.

Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography

Problem Statement: Arithmetic Logic Unit (ALU) of a crypto-processor and microchips leak information through power consumption. Although the cryptographic protocols are secured against mathematical attacks, the attackers can break the encryption by measuring the energy consumption. Approach: To thwart attacks, this study proposed the use of reversible logic for designing the ALU of a crypto-processor. Ideally, reversible circuits do not dissipate any energy. If reversible circuits are used, then the attacker would not be able to analyze the power consumption. In order to design the reversible ALU of a crypto-processor, reversible Carry Save Adder (CSA) using Modified TSG (MTSG) gates and architecture of Montgomery multiplier were proposed. For reversible implementation of Montgomery multiplier, efficient reversible multiplexers and sequential circuits such as reversible registers and shift registers were presented. Results: This study showed that modified designs perform better than the existing ones in terms of number of gates, number of garbage outputs and quantum cost. Lower bounds of the proposed designs were established by providing relevant theorems and lemmas. Conclusion: The application of reversible circuit is suitable to the field of hardware cryptography.

Accelerating Integer Neural Networks On Low Cost DSPs

In this paper, low end Digital Signal Processors (DSPs) are applied to accelerate integer neural networks. The use of DSPs to accelerate neural networks has been a topic of study for some time, and has demonstrated significant performance improvements. Recently, work has been done on integer only neural networks, which greatly reduces hardware requirements, and thus allows for cheaper hardware implementation. DSPs with Arithmetic Logic Units (ALUs) that support floating or fixed point arithmetic are generally more expensive than their integer only counterparts due to increased circuit complexity. However if the need for floating or fixed point math operation can be removed, then simpler, lower cost DSPs can be used. To achieve this, an integer only neural network is created in this paper, which is then accelerated by using DSP instructions to improve performance. Keywords—Digital Signal Processor (DSP), Integer Neural Network (INN), Low Cost Neural Network, Integer Neural Network DSP Implementation.

Simulation Study on the Effect of Multiple Node Charge Collection on Error Cross-Section in CMOS Sequential Logic

A technique for estimating error cross-section for combinational circuits based on charge collection at multiple nodes is presented. Ordinarily, charge collection from an ion strike is assumed to occur only on a single node, but with decreasing feature sizes in nanometer technologies, charge sharing among devices is worsening, leading to charge collection on multiple nodes. When multiple SETs are considered, simulation results show a 380times increase in cross-section with a four-bit carry look-ahead generator, and a 27times increase with a four-bit arithmetic logic unit. Additionally, both circuits show a linear increase in cross-section as frequency increases.

Closed Fragments of Provability Logics of Constructive Theories

AbstractIn this paper we give a new proof of the characterization of the closed fragment of the provability logic of Heyting's Arithmetic. We also provide a characterization of the closed fragment of the provability logic of Heyting's Arithmetic plus Markov's Principle and Heyting's Arithmetic plus Primitive Recursive Markov's Principle.