A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regularnanowire network with hexagonal topology

Abstract

A two-bit arithmetic logic unit (ALU) was successfully fabricated on a GaAs-based regularnanowire network with hexagonal topology. This fundamental building block of centralprocessing units can be implemented on a regular nanowire network structure with simplecircuit architecture based on graphical representation of logic functions using a binarydecision diagram and topology control of the graph. The four-instruction ALU wasdesigned by integrating subgraphs representing each instruction, and the circuitry wasimplemented by transferring the logical graph structure to a GaAs-based nanowirenetwork formed by electron beam lithography and wet chemical etching. A pathswitching function was implemented in nodes by Schottky wrap gate control ofnanowires. The fabricated circuit integrating 32 node devices exhibits the correctoutput waveforms at room temperature allowing for threshold voltage variation.