Arithmetic Logic Research Articles

DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS

Arithmetic Logic Unit is the brain of all processors, is composed of an Adder circuit. The main component of multiplier circuits is the adder, which performs subtraction (by 2’s complement arithmetic). Since the most fundamental operation in mathematics is addition, and the adder is the most essential part of the processor, the study of VLSI arithmetic has required many digital VLSI researchers. When designing digital systems employing the VLSI approach, the digital adder plays a major role. Low power VLSI based adder designs perform poorly because of the propagation delay issue. With the aid of the PPA design, an assessment of adders’ availability for low power VLSI designs with minimal propagation delay is conducted. Using these performance measures, this study compares and evaluates the performance of several parallel prefix adders, allowing readers to select the optimum adder architecture for their application Specific Integrated Circuits implementations. The three adder topologies taken into considered in this Article include the Han carlson adder, Brent kung, Kogge stone adders. Xilinx ZYNQ XC7Z020 (7000 series) SoC is used to implement the adders using the Vivado Design Suite 2014 and Verilog.

Efficient 3’s Complement Circuit for Ternary-ALU

Carrying more information makes the ternary-computation effective in order to reduce the interconnect complexity and hence, ternary computer can be the future alternative to conventional (binary) counterpart. As a consequence the ternary arithmetic has become the centre of choice among circuit/system researcher in recent time. Ternary adder/subtractor is the integral part of Ternary Arithmetic Logic Unit (TALU) and the 3’s complement is used to represent negative ternary number in TALU. This work proposes a new two-step low hardware-cost strategy to converts ternary input into its 3’s complement output. Novel hardware optimization using normal process Enhancement-type Metal Oxide Semiconductor (E-MOS)-transistor is explored and exploited to design proposed 4-trit 3’s complement generator on 32nm standard CMOS technology with 0.9V supply-rail at 27°C temperature using typical MOS-transistor. Unbalanced ternary digit “0”, “1” and “2” are denoted with ground, supply/2 and supply respectively. The T-Spice transient simulations with all possible test patterns validate the working of proposed circuit and the corresponding speed-power characteristic is compared with most recent counterpart. The circuit performance is also evaluated with different load condition. The 4-trit 3’s complement circuit is extended next to propose 16-trit 3’s complement generator and the impact of Process and Environmental variation on the proposed circuit is studied.

XVDPU: A High-Performance CNN Accelerator on the Versal Platform Powered by the AI Engine

Today, convolutional neural networks (CNNs) are widely used in computer vision applications. However, the trends of higher accuracy and higher resolution generate larger networks. The requirements of computation or I/O are the key bottlenecks. In this article, we propose XVDPU: the AI Engine (AIE)-based CNN accelerator on Versal chips to meet heavy computation requirements. To resolve the IO bottleneck, we adopt several techniques to improve data reuse and reduce I/O requirements. An arithmetic logic unit is further proposed that can better balance resource utilization, new feature support, and efficiency of the whole system. We have successfully deployed more than 100 CNN models with our accelerator. Our experimental results show that the 96-AIE-core implementation can achieve 1,653 frames per second (FPS) for ResNet50 on VCK190, which is 9.8× faster than the design on ZCU102 running at 168.5 FPS. The 256-AIE-core implementation can further achieve 4,050 FPS. We propose a tilling strategy to achieve feature-map-stationary for high-definition CNN with the accelerator, achieving 3.8× FPS improvement on the residual channel attention network and 3.1× on super-efficient super-resolution. This accelerator can also solve the 3D convolution task in disparity estimation, achieving end-to-end performance of 10.1 FPS with all the optimizations.

CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analysed using the Cadence Spectre.

Vector Accelerator Unit for Caravel

Caravel is an open-source project developed by Efabless for creating custom System-on-Chips (SoCs). It includes the design of a configurable chip, development tools, and documentation. The Caravel SoC includes a RISC-V with the Instruction Set Architecture RV32I. One of the key features of Caravel is its open-source nature. In this article, the Vector Accelerator Unit for the Caravel SoC template is presented to increase the RISC-V capabilities, allowing parallel data processing through 14 vector operations. The accelerator is based on 4 Arithmetic Logic Units connected directly to the RISC-V through Logic Analyzer port and the General-Purpose Input/Output (GPIO) port. The total area of this accelerator is less than 20% of the User Project Wrapper area allowing the user to implement their custom designs in 8.4256 mm.

Enhancing ASIC chip performance through integrated algorithm optimization

As a crucial arithmetic logic unit, the multiplier plays a significant role in digital signal processing. However, multiplication operations often require a large number of calculations and logic gates, leading to increased circuit complexity and power consumption. To enhance the performance and efficiency of multipliers, this paper presents an optimization analysis based on the Wallace Tree and Booth algorithms. The Wallace Tree algorithm decomposes multiplication operations into multiple stages and employs both separate operations and bit-level parallelism to accelerate multiplication, achieving efficient parallel multiplication computations and reducing both latency and area complexity of multiplication. On the other hand, the Booth algorithm is an optimization method for signed binary multiplication. By introducing the concept of Booth encoding, it transforms signed multiplication into unsigned multiplication, thereby reducing the number of multiplication operations. This paper analyses the application and research progress of the Wallace Tree and Booth algorithms in the field of multiplier optimization to improve computational speed and reduce power consumption of multipliers.

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442 nW and 0.323 nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.

A new nano-design of configurable logic module based on coplanar reversible adder and modified Fredkin gates using quantum technology

Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications.

Design a 5-stage pipeline RISC-V CPU and optimise its ALU

The RISC-V instruction set has advanced and expanded significantly in recent years. It is an open instruction set architecture (ISA) based on the concept of Reduced Instruction Set Computing (RISC). This article uses Verilog to design a 5-stage pipeline CPU based on RISC-V architecture in Vivado 2022.2. The CPU can execute 38 instructions and optimises its arithmetic logic unit (ALU) by optimising adders, shifters, and multipliers. Next, write a testbench in the simulation software to verify the functionality of the CPU. RTL diagrams and reports are then generated to verify the design structure and evaluate resource allocation. Finally, the CPU successfully executes the instruction and obtains the correct operation result, and the occupation of LUT resources in the shifter part is reduced. This work serves as an important reference for system-on-chip (SoC) and computer design in general. It not only highlights the potential of the RISC-V architecture but also demonstrates the success of optimisation efforts. This paves the way for more powerful and efficient computing systems.

The Mechanism of The Arithmetic Logic Unit

The Arithmetic Logic Unit is widely used in electrical components nowadays such as the CPU in computers. The traditional research is based on the theory of a combination of multiple logic units, the results are not performed intuitional. This paper provides an introduction to the Arithmetic Logic Unit and its mechanisms, which consist of multiple logic gates to perform binary operations and send commands to the computer. The article discusses binary operations using logic gates, starting from the simplest one-bit half-adder to the more complex four-bit ALU, encompassing functions like addition, subtraction, division, and multiplication. The simulation module is used to justify the mechanism of the ALU. This research provides a new method in the process of developing the ALU, may largely increases the productivity. The approach may be used in the research and development of computer performance, providing visual, instant feedback and reducing the cost.

Arithmetic logic unit based on the metastructure with coherent absorption: erratum.

We present a corrigendum to our Letter [Opt. Lett.48, 5699 (2023)10.1364/OL.505761]. In section 3 of the original supplementary material, the absolute value is incorrectly taken in resolving the Kubo formula for describing the conductivity of graphene. Because this is a mistake with the conductivity of graphene, the coupling of the original structure is broken when the correct result is inserted into the code of the transfer matrix. So, the structure of the arithmetic logic unit (ALU), characteristic frequency point, and phase control have been modified accordingly. However, the ultimate function and the conclusion of this work remain unchanged.

An Optimized Hardware Implementation of a Non-Adjacent Form Algorithm Using Radix-4 Multiplier for Binary Edwards Curves

Binary Edwards Curves (BEC) play a pivotal role in modern cryptographic processes and applications, offering a combination of robust security as well as computational efficiency. For robust security, this article harnesses the inherent strengths of BEC for the cryptographic point multiplication process by utilizing the Non-Adjacent Form (NAF) algorithm. For computational efficiency, a hardware architecture for the NAF algorithm is proposed. Central to this architecture is an Arithmetic Logic Unit (ALU) designed for streamlined execution of essential operations, including addition, squaring, and multiplication. One notable innovation in our ALU design is the integration of multiplexers, which maximize ALU efficiency with minimal additional hardware requirements. Complementing the optimized ALU, the proposed architecture incorporates a radix-4 multiplier, renowned for its efficiency in both multiplication and reduction. It eliminates resource-intensive divisions, resulting in a substantial boost to overall computational speed. The architecture is implemented on Xilinx Virtex series Field-Programmable Gate Arrays (FPGAs). It achieves throughput-to-area ratios of 14.819 (Virtex-4), 25.5 (Virtex-5), 34.58 (Virtex-6), and 37.07 (Virtex-7). These outcomes underscore the efficacy of our optimizations, emphasizing an equilibrium between computational performance and area utilization.

Quantum Fourier Transform‐Based Arithmetic Logic Unit on a Quantum Processor

AbstractThis study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two‐input and four‐input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform‐based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft‐core processor on a quantum processing unit.

Design and implementation of an 8-bit ALU based on verilog HDL

Many modern processors incorporate an Arithmetic Logic Unit (ALU) as an integral component. The ALU plays a pivotal role in arithmetic and logical operations, making it a fundamental block in processor architecture. Utilizing software tools like Quartus II and ModelSim, one can seamlessly design, implement, and simulate an 8-bit ALU. This research focuses on creating an ALU that can perform a broad range of operations, including Addition, Subtraction, Multiplication, Division, Shifting, Rotation, AND, OR, XOR, NOR, NAND, XNOR, and Comparison. With these 16 operations in mind, the ALUs circuitry was meticulously crafted using Quartus II. To validate its functionality and performance, joint simulations were conducted with both Quartus II and ModelSim. As a result, comprehensive simulation waveforms were derived, offering insights into the ALUs behavior and response for each instruction. These waveforms serve as a testament to the ALUs robust design and provide a foundation for further analysis and optimization.

A Machine Learning-Based Short-Circuit Power Prediction at Floorplan Stage of IC Physical Design

This work is devoted to the study of the use of machine learning (ML) to predict short-circuit power consumption at the floorplan stage of the physical design of integrated circuits. The study was carried out for 4 cell groups: registers, combinational cells, sequential cells, and cells included in the clock network. An Arithmetic Logic Unit was selected and designed to create a database necessary for the training and testing of ML models. The design is carried out for various combinations of parameters. Input parameters for training models are supply voltage, temperature, clock frequency, library type based on threshold voltage, block utilization and block aspect ratio. The output parameters are the values of short-circuit power after gate level simulation, considering the parasitic parameters. In total, five algorithms were tested: Polynomial Regression, Decision Tree Regression, Random Forest Regression, Supported Vector Regression (SVR) and Multi-layer Perceptron (MLP). Root Mean Squared Error, R2 and Mean Absolute Percentage Error (MAPE) metrics were used to evaluate the performance of the models. The MLP showed the best performance, but the SVR algorithm with standardization of output parameters showed similar results with significantly less training time. The MAPE value for registers is » 0,89 %, for combinational cells » 3,19 %, for sequential cells » 2,42 % and for the clock network cells » 9,55 %. The proposed method of model training is not based on any technology-dependent data, which makes it universal for different technology nodes. The disadvantage of the method is the need for implementation of the whole design flow for a selected design with the selected range of parameters for collecting necessary training data, which requires additional time and machine resources.

Nanomaterials in Nanophotonics Structure for Performing All-Optical 2 × 1 Multiplexer Based on Elliptical IMI-Plasmonic Waveguides

In this study, an all-optical multiplexer (Mux) based on elliptical insulator-metal-insulator (IMI) plasmonic waveguides is designed. The area of the proposed structure is very small (400 nm × 400 nm) which operates at a wavelength of 1,550 nm. The developed device utilizes constructive and destructive interferences between the input signals and the selector signal. This structure is less complex and has lower loss compared to the previous works. Transmission (T), contrast ratio (CR), modulation depth (MD), insertion loss (IL), and contrast loss (CL) are the five parameters that describe the performance of the plasmonic Mux. The transmission threshold between logic 0 and logic 1 is 0.5. Moreover, the maximum transmission efficiency of the device is 163%. Moreover, based on the MD value of 95.09%, the dimensions of the proposed structure are excellent and optimal. The proposed plasmonic Mux structure contributes substantially to developing an all-optical arithmetic logic unit (ALU) and all-optical signal processing nanocircuits. The finite element method (FEM) simulates the proposed plasmonic multiplexer with COMSOL Multiphysics 5.4 software.

A Compilation Tool for Computation Offloading in ReRAM-based CIM Architectures

Computing-in-Memory (CIM) architectures using Non-volatile Memories (NVMs) have emerged as a promising way to address the “memory wall” problem in traditional Von Neumann architectures. CIM accelerators can perform arithmetic or Boolean logic operations in NVMs by fully exploiting their high parallelism for bit-wise operations. These accelerators are often used in cooperation with general-purpose processors to speed up a wide variety of artificial neural network applications. In such a heterogeneous computing architecture, the legacy software should be redesigned and re-engineered to utilize new CIM accelerators. In this article, we propose a compilation tool to automatically migrate legacy programs to such heterogeneous architectures based on the low-level virtual machine (LLVM) compiler infrastructure. To accelerate some computations such as vector-matrix multiplication in CIM accelerators, we identify several typical computing patterns from LLVM intermediate representations , which are oblivious to high-level programming paradigms. Our compilation tool can modify accelerable LLVM IRs to offload them to CIM accelerators automatically, without re-engineering legacy software. Experimental results show that our compilation tool can translate many legacy programs to CIM-supported binary executables effectively, and improve application performance and energy efficiency by up to 51× and 309×, respectively, compared with general-purpose x86 processors.

Chatbots Put to the Test in Math and Logic Problems: A Comparison and Assessment of ChatGPT-3.5, ChatGPT-4, and Google Bard

In an age where artificial intelligence is reshaping the landscape of education and problem solving, our study unveils the secrets behind three digital wizards, ChatGPT-3.5, ChatGPT-4, and Google Bard, as they engage in a thrilling showdown of mathematical and logical prowess. We assess the ability of the chatbots to understand the given problem, employ appropriate algorithms or methods to solve it, and generate coherent responses with correct answers. We conducted our study using a set of 30 questions. These questions were carefully crafted to be clear, unambiguous, and fully described using plain text only. Each question has a unique and well-defined correct answer. The questions were divided into two sets of 15: Set A consists of “Original” problems that cannot be found online, while Set B includes “Published” problems that are readily available online, often with their solutions. Each question was presented to each chatbot three times in May 2023. We recorded and analyzed their responses, highlighting their strengths and weaknesses. Our findings indicate that chatbots can provide accurate solutions for straightforward arithmetic, algebraic expressions, and basic logic puzzles, although they may not be consistently accurate in every attempt. However, for more complex mathematical problems or advanced logic tasks, the chatbots’ answers, although they appear convincing, may not be reliable. Furthermore, consistency is a concern as chatbots often provide conflicting answers when presented with the same question multiple times. To evaluate and compare the performance of the three chatbots, we conducted a quantitative analysis by scoring their final answers based on correctness. Our results show that ChatGPT-4 performs better than ChatGPT-3.5 in both sets of questions. Bard ranks third in the original questions of Set A, trailing behind the other two chatbots. However, Bard achieves the best performance, taking first place in the published questions of Set B. This is likely due to Bard’s direct access to the internet, unlike the ChatGPT chatbots, which, due to their designs, do not have external communication capabilities.

Arithmetic logic unit based on the metastructure with coherent absorption.

An arithmetic logic unit (ALU) based on the metastructure (MS) with coherent absorption (CA) is proposed in this Letter. The ALU can perform AND and exclusive OR logical operations at the same frequency point. So it can be regarded as an optical half-adder. By controlling the chemical potential of graphene and the phase difference of coherent electromagnetic waves (EWs), two different binary numbers are input into the ALU. The dynamic absorption peaks, which are generated based on the CA, output the outcomes of the carry-digit bit and non-carry sum bit. This ALU can be used in the field of optical processing and encryption, such as processing hamming code. This given ALU based on the MS with CA has major implications for advancing the study and investigation into the application of CA. Furthermore, it also provides a new, to the best of our knowledge, idea for the study of MS with logical operation.

Design and Implementation of 12-Bit Arithmetic Logic Unit with 8 Operation Codes to Field Programmable Gate Array

Digital system has been a part of human life since the invention of the computer with a microprocessor as the central brain. At the heart of a processor is an Arithmetic Logic Unit (ALU) that handles arithmetic and logic operations. The need for high-speed computation to handle complex computations demands microprocessors with higher performance. The existing 4-opcode 8-bit ALU cannot handle multiplication operations, so a solution is needed. In this research, while raising the appeal of beginners, a 12-bit ALU with eight operation codes (opcode) was designed and implemented in Xilinx’s Field Programmable Gate Array using a schematic diagram approach through logic gates. The designed and implemented ALU provides addition, subtraction, multiplication, square, AND, OR, NAND, and XOR operations. The multiplication operation was tested by performing the computation to provided datasets to obtain the distance travelled by ten military aircraft based on their maximum speed and air travel duration to ensure its performance. The computation performance comparison with an 8-bit ALU with four opcodes was also done. The computation was done for air travel between 10 to 60 minutes with a 10-minute difference. It was found that the 12-bit ALU with eight opcodes outperformed its contender with computation differences between 130.815 ns and 1,468.214 ns. This high performance is supported by the multiply operation that does repeated addition at one time. Based on this finding, the 8-opcode 12-bit ALU is more efficient in the context of computation time, with consistent accuracy. Moreover, the computation time required to calculate military aircraft data with different maximum speeds and air travel duration is only 119.501 ns.