Vector Accelerator Unit for Caravel

Abstract

Caravel is an open-source project developed by Efabless for creating custom System-on-Chips (SoCs). It includes the design of a configurable chip, development tools, and documentation. The Caravel SoC includes a RISC-V with the Instruction Set Architecture RV32I. One of the key features of Caravel is its open-source nature. In this article, the Vector Accelerator Unit for the Caravel SoC template is presented to increase the RISC-V capabilities, allowing parallel data processing through 14 vector operations. The accelerator is based on 4 Arithmetic Logic Units connected directly to the RISC-V through Logic Analyzer port and the General-Purpose Input/Output (GPIO) port. The total area of this accelerator is less than 20% of the User Project Wrapper area allowing the user to implement their custom designs in 8.4256 mm.