Arithmetic Unit Research Articles

Implementation of adders using XOR gates in quantum-dot cellular automata with physical verification

Abstract This paper presents a promising approach to nanoscale computing, offering significant advantages through the QCA technology. It suggests a highly efficient, scalable, and reliable multilayered QCA half and full adder circuits, leveraging a three-input QCA XOR gate. The proposed full adder layout demonstrates significant improvements in various parameters, including area, latency, and energy dissipation. In particular, it offers 17% greater area efficiency and utilizes 14 fewer cells compared to the best work existing work. We thoroughly evaluated energy dissipation using the QCADesigner-E tool. We also examined the cost functions, with a QCA-specific cost of 22 units, which is ~37% better than earlier designs. The architecture is strategically designed with externally accessible input and output nodes to ensure seamless scalability. Physical reliability is ensured through kink energy calculations for the suitability of higher-order circuit designs. Practical applications of the proposed blocks include their use in arithmetic logic units (ALUs), digital signal processors, and other modern processing and computing systems. This work sets a new benchmark for future developments in QCA technology, offering a robust, efficient, and versatile solution for advanced nano-processing and computing systems.

Analog Implementation of a Spiking System for Performing Arithmetic Logic Operations on Mixed‐Signal Neuromorphic Processors

In recent years, physical limitations in the integration of transistors in computers have forced the search for low‐computational‐power alternatives in hardware design. Although doubts may arise regarding the limit of the relationship between performance and power consumption in computers, these disappear when considering the brain, which is one of the most efficient computing systems. In this way, bioinspired applications try to benefit from the low‐power consumption present in the biological nervous system. Previous work has shown the feasibility of implementing spiking neural networks that operate in a Boolean manner on digital platforms, such as SpiNNaker, using basic logic gates and a spiking memory, which suggests the potential for constructing a low‐power consumption spiking computer. This work takes a first step in the implementation of a spiking central processing unit by developing an arithmetic logic unit, which is an essential block for instruction execution, demonstrating its correct operation on Dynap‐SE1. The results confirm the feasibility of using this Boolean approach on this platform, despite certain limitations in the number of inputs and operating frequencies of the blocks, and pave the way for the construction of a spiking computer.

Prepare Linear Distributions with Quantum Arithmetic Units

Quantum arithmetic logic units (QALUs) perform essential arithmetic operations within a quantum framework, serving as the building blocks for more complex computations and algorithms in quantum computing. In this paper, we present an approach to prepare linear probability distributions with quantum full adders. There are three main steps. Firstly, Hadamard gates are applied to the two input terms, preparing them at quantum states corresponding to uniform distribution. Next, the two input terms are summed up by applying quantum full adder, and the output sum is treated as a signed integer under two’s complement representation. By the end, additional phase −1 is introduced to the negative components. Additionally, we can discard either the positive or negative components with the assistance of the Repeat-Until-Success process. Our work demonstrates a viable approach to prepare linear probability distributions with quantum adders. The resulting state can serve as an intermediate step for subsequent quantum operations.

Investigation of PNN Inverter-Based Low PDP 12T GNRFET Full Adder for VLSI Signal Processing Applications

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16[Formula: see text]nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16[Formula: see text]nm MOS-GNRFET model.

Efficient quantum-dot adder optimisation and analysis for future circuits

ABSTRACT In recent years, the rapid scaling of transistors has necessitated the exploration of advanced alternatives to Complementary metal oxide semiconductor(CMOS) technology for future progress. Quantum-dot cellular automata(QCA) technology has emerged as a promising solution, offering highly dense, high-speed, and low-power circuits. Among the critical digital building blocks, adder circuits play a crucial role in arithmetic and logic units. Consequently, optimising these circuits in terms of area, delay, and quantum cost is essential for the development of efficient designs. This paper presents effective multi-layer n-bit ripple carry adder(RCA) circuits, utilising full adder(FA) circuit. The outputs are generated in distinct layers and verified using the QCADesigner-Ev2.2 tool with bi-stable and coherence vector energy setups, employing Euler and Runge-Kutta methods.Additionally, the proposed designs are evaluated for various design metrics at three different scale factors(1,0.8889,and 0.7778), corresponding to cell sizes of 18 × 18 nm , 16 × 16 nm , and 14 × 14 nm respectively. The temperature’s impact on the average output polarisation of the FA is explored. The research demonstrates an n-bit-RCA surpassing existing designs with cost optimisations of 89.5%, 86%, and 90.3% for 4-bit,8-bit and 16-bit circuits, respectively. The paper also provides a thorough energy dissipation analysis for the proposed adder design.

Multi-Layer QCA Reversible Full Adder-Subtractor Using Reversible Gates for Reliable Information Transfer and Minimal Power Dissipation on Universal Quantum Computer

The effects of quantum mechanics dominate nanoscale devices, where Moore’s law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization.

Research on Multiplication Routine Based on Reconfigurable Four-Valued Logic Processor

Despite the indispensable role of traditional electronic computers in modern society, their limitations in parallel processing capabilities, bit-width constraints, and processor bit-width are becoming increasingly apparent, especially when handling large-scale datasets and complex computational tasks. Although hardware technology and algorithm optimization continue to advance, the arithmetic units of traditional computers—adders—remain constrained by carry delay and bit-width limitations. This bottleneck is particularly pronounced in multiplication operations, mainly when adders are used for partial product accumulation. However, since 2018, the emergence of a new type of Reconfigurable Four-Valued Logic Electronic Processor (RFLEP) has provided a potential solution to these traditional limitations. With its large processor bit-width, flexible bit grouping capabilities, and dynamic hardware function reconfiguration features, this processor has brought revolutionary changes to the field of computing. In this context, this paper proposes and implements a Reconfigurable Four-Valued Logic Multiplication Routine (RFLMR) tailored explicitly for the RFLEP. The RFLMR utilizes the Modified Signed-Digit (MSD) representation method in multi-valued logic combined with the M transformation in four-valued logic to generate partial products. These partial products are then efficiently summed in parallel using the JW-MSD parallel adder, achieving the rapid execution of multiplication operations. Experimental results demonstrate that the multiplication routine based on the RFLEP performs multiplication operations accurately and meets theoretical expectations regarding implementation efficiency and performance. This research not only provides new ideas for developing next-generation high-performance computing systems but also paves the way for exploring more efficient and powerful computing models, heralding a profound transformation in future computing technology.

Layered heterogeneous structures integrated device for multiplication, division arithmetic unit and multiple-physical sensing

A layered heterogeneous structure (LHS), consisting of silver, liquid crystal, and nonlinear dielectric layers, is proposed to realize functions of computing and sensing. By leveraging the optical Tamm state, the intrinsic absorption principle of liquid crystal, and nonlinear effects, the design of an integrated device capable of passive multiplication and division operations, along with high-performance multi-physical quantity sensing functionalities, is achieved. The given LHS exhibits Janus properties, with different physical functions manifested depending on the direction of electromagnetic wave (EW) propagation. During forward propagation of EWs, the LHS displays high and sharp absorptivity peaks at 774.8 and 1517.6 nm. The relationship between the two peaks approximates a frequency multiplication factor of 1.960, enabling signal multiplication. Furthermore, the two absorptivity peaks at different wavelengths facilitate the sensing of serum creatinine solution concentration and external pressure, with sensitivity (S), quality factors (Q), and figure of merit (FOM) of 266.76 μmol L−1/nm and 213.33 GPa/nm, as well as 248.76 and 348.22, 84.1 L (μmol)−1 and 49.06 GPa−1, respectively. During backward propagation of EWs, absorptivity peaks with distinct resolutions are observed at 1423 and 2809 nm, with a multiple relationship between them of 1.974, enabling frequency doubling for signal division. Additionally, the absorptivity curve facilitates temperature sensing over a wide range from 257 to 347 K. Owing to the unique temperature S of liquid crystal, different sensitivities and resolutions are observed at 257 to 297 K and 307 to 347 K, with S of 1.015 and 0.686 K/nm, and corresponding Q and FOM of 21.57 and 12.576, 0.076 K−1 and 0.003 04 K−1, respectively.

Reversible arithmetic and logic unit using a novel reversible NRRG gate in quantum dot technology

Quantum-dot Cellular Automata (QCA) has become one of the promising studies for nano-scale computing. QCA is one of the candidate technologies to be replaced with CMOS technology. QCA technology not only reduces power consumption and delay but also increases operating frequency and speed. The arithmetic logic unit is the essential component in a processor that performs arithmetic and logical operations. This paper presents a novel 5 × 5 reversible logic gate called the NRRG (Norouzi_Rasouli Reversible Gate) which can be used as the basic building block of 4:1 and 8:1 reversible multiplexers. Then, we have designed a RALU (reversible arithmetic and logic unit) using this gate. Our design can perform 20 operations such as AND, NAND, OR, XOR, XNOR, COPY, addition, and increment. The proposed QCA RALU requires 0.44 μm2 area, 480 QCA cells, and 10 clock phases. The proposed design needs less cell count, delay, and cost of QCA compared to previous works. The structure is implemented without any rotated cells and only uses one layer which improves the manufacturability of the design. The architectures are designed and simulated using QCA Designer 2.0.3.

Design of Energy Efficient Arithmetic VLSI Circuits

Advanced electronics have become an integral part of human lives, from Smartphones in our pockets to the modern vehicles on the road and to the satellites that orbit the earth. Power consumption has become a major constraint in these applications, often employing data- intensive digital signal processing systems and architectures. While enormous transistor density at the nanoscale has been increased in the Very Large-Scale Integration (VLSI) multicore era comparable to Moore's law, improving the performance of computing systems has become extremely difficult. Sustaining technological advancements for such energy-constrained devices has paved the way for new areas in research. “Approximate Computing (AC)” has become one of the most promising paradigms, a field that has gainedsignificant attention in the quest for energy efficiency in recent years. AC algorithms are numerically approximate rather than accurate. Inherent error resilience is the primary source of motivation behind AC. Recent research demonstrates that error resilience is pervasive in cyber search, deep learning, multimedia, recognition and data mining. Arithmetic units are the fundamental building blocks in most of the data dominated applications at the micro- architectural level of abstraction. AC is optimal for power and area efficient arithmetic circuits.

Design of a novel low-latency parameterizable posit adder/subtractor using leading one predictor in FPGA

Posit arithmetic has attracted a lot of attention as a promising alternative to the IEEE754 floating-point number representation thanks to its advantages such as higher accuracy and dynamic range. However, hardware solutions are not yet mature, as the posit number representation is still in its infancy. Therefore, posit units are more expensive and low performance than IEEE754 floating-point units. In this paper, a parameterizable low-latency posit adder/subtractor architecture is proposed, which contributes to higher performance posit arithmetic units. Normalization, which is quite slow in standard posit adder/subtractor architectures, is accelerated. The leading-one prediction algorithm is used to determine the amount of left shift required for normalization which reduces the delay time by shortening the critical path. Proposed and standard posit adder/subtractor architectures are implemented on Xilinx Zynq 7000 SoC XC7Z020-CLG484–1 chip with exponent bit length 1, 2, 3 and 4 and precision 16, 32, 64 and 128. The proposed adder/subtractor architecture has lower delay time than the standard architecture at 32, 64 and 128 bits. The results show that the proposed posit adder/subtractor has a lower delay time than the standard design by 0.417 ns, 0.398 ns and 2.636 ns for 32, 64 and 128 bits precision, respectively.

Design of All-Optical D Flip Flop Memory Unit Based on Photonic Crystal.

This paper proposes a unique configuration for an all-optical D Flip Flop (D-FF) utilizing a quasi-square ring resonator (RR) and T-Splitter, as well as NOT and OR logic gates within a 2-dimensional square lattice photonic crystal (PC) structure. The components realizing the all-optical D-FF comprise of optical waveguides in a 2D square lattice PC of 45 × 23 silicon (Si) rods in a silica (SiO2) substrate. The utilization of these specific materials has facilitated the fabrication process of the design, diverging from alternative approaches that employ an air substrate, a method inherently unattainable in fabrication. The configuration underwent examination and simulation utilizing both plane-wave expansion (PWE) and finite-difference time-domain (FDTD) methodologies. The simulation outcomes demonstrate that the designed waveguides and RR effectively execute the operational principles of the D-FF by guiding light as intended. The suggested configuration holds promise as a logic block within all-optical arithmetic logic units (ALUs) designed for digital computing optical circuits. The design underwent optimization for operation within the C-band spectrum, particularly at 1550 nm. The outcomes reveal a distinct differentiation between logic states '1' and '0', enhancing robust decision-making on the receiver side and minimizing logic errors in the photonic decision circuit. The D-FF displays a contrast ratio (CR) of 4.77 dB, a stabilization time of 0.66 psec, and a footprint of 21 μm × 12 μm.

Field-programmable gate array implementation of efficient deep neural network architecture

Deep neural network (DNN) comprises multiple stages of data processing sub-systems with one of the primary sub-systems is a fully connected neural network (FCNN) model. This fully connected neural network model has multiple layers of neurons that need to be implemented using arithmetic units with suitable number representation to optimize area, power, and speed. In this work, the network parameters are analyzed, and redundancy in weights is eliminated. A pipelined and parallel structure is designed for the fully connected network information. The proposed FCNN structure has 16 inputs, 3 hidden layers, and an output layer. Each hidden layer consists of 4 neurons and describes how the inputs are connected to hidden layer neurons to process the raw data. A hardware description language (HDL) model is developed for the proposed structure and the verified model is implemented on Xilinx field-programmable gate array (FPGA). The modified structure comprises registers, demultiplexers, weight registers, multipliers, adders, and read-only memory lookup table (ROM/LUT). The modified architecture implemented on FPGA is estimated to reduce area by 87.5% and improve timing by 3x compared with direct implementation methods.

ASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit

ASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit

Dynamic Power Saving for CMOS Circuits

With more functionalities being integrated into a microchip today, higher processing power is drawn. As a result of this, clock and logic power consumption has turned out to be a critical issue to be coped with by chip designers. In this paper, we present various power-saving approaches employed in complementary metal oxide semiconductor (CMOS) circuit designs. The approaches involve restructuring the logic circuits, performing clock gating, and selecting the appropriate circuits for counters and frequency divisions. In order to show their efficacies in power optimization, the approaches were applied to a phase-locked loop (PLL), clock divider (CD), full adder (FA), counter, arithmetic logic unit (ALU), and microprocessor without interlocked pipelined stages (MIPS) circuits and validated using Intel Quartus Prime Lite and Mentor Graphics Modelsim. The following conclusions can be drawn from the results: Firstly, the efficacy of minimizing power dissipation using logic restructuring is found to be in direct proportion with the rate of the switching activity (SA); secondly, a maximum of 3.5% of thermal power dissipation can be saved using clock gating; thirdly, gray counters give the lowest power consumption; and, finally, the thermal power estimation for the phase-locked loop (PLL) is relatively higher than that for the clock divider (CD) when both of them are implemented for dividing frequencies.

Design and Implementation of a 2-input Arithmetic and Logic Unit using Quantum-dot Cellular Automata

Quantum-Dot-Cellular Automata (QCA), an emerging nanotechnology rooted in Coulomb repulsion, holds the ability to supplant orthodox complementary metal-oxide semiconductor (CMOS) technology. Its distinctive advantages lie in ultra-low power consumption, fast switching speed, and high-density structures. This study conducts an extensive literature review to introduce an Arithmetic and Logic Unit (ALU) based on QCA principles. The proposed QCA-based ALU incorporates fundamental logic gates, adders, and subtractors, leveraging the latest XOR gate. Utilizing simulation via QCA Designer 2.0.3, an in-depth performance evaluation of the model is conducted, comparing it with established ALUs based on metrics encompassing cell count, delay, and area. The findings showcase the efficiency of the proposed ALU, characterized by its minimal requirement of 277 cells, an area occupancy of 0.43 µm², and a delay of 2.75 clock cycles. This outcome highlights the favorable attributes of our design compared to existing alternatives, suggesting its potential contribution to the advancement of QCA-based digital circuitry. DUJASE Vol. 8 (1) 26-31, 2023 (January)

A comprehensive analysis of ultra low power GNRFET based 20T hybrid full adder for computing applications

In an era where energy efficiency is as important as computational speed, this paper introduces a new full adder circuit design that effectively integrates dynamic power gathering (DPG) power conservation benefits with XOR-XNOR pass-transistor logic (PTL) area and performance efficiencies using graphene nanoribbon field-effect transistors. GNRFETs are useful for digital logic due to their high carrier mobility and tunable bandgap. The paper describes the circuit’s seamless transition full adder response, demonstrating the tri-mode dynamic power gating strategy capacity to reduce static power depletion. The proposed hybrid full adder performs well with 7.76 nW power consumption, 481 ps latency, and 3.73 aJ PDP. This reduces power consumption by 99.9%, delay by 99.0%, and PDP by 99.8% compared to other adders. The effects of temperature, voltage, Noise immunity and Carry Forward Adders integration on power, delay, and PDP are also analysed, proving the design’s robustness. The adaptability of our full adder architecture allows its implementation in more complicated arithmetic and logic units, indicating a scalable and energy-efficient paradigm for future integrated circuits.

Design and Implementation of 1-bit Full Subtractor Using FinFET

Abstract: A full subtractor is a digital combinational circuit that performs subtraction involving three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout (borrow out). Unlike a half adder, which adds only two binary digits and produces a sum and carry, a full adder considers an additional carry input from a previous less significant bit addition. The full adder's design includes three inputs: A, B, and Cin (carry-in), and two outputs: Sum (sum) and Cout (carry-out). The sum output Sum is derived by XOR-ing the three inputs, while the carry-out Cout is obtained by considering the majority function of the inputs. This means Cout is set when any two or more of the three inputs are high (logical 1). Full subtractors are fundamental components in the construction of arithmetic logic units (ALUs), binary adders, and other computational circuits in digital systems, enabling the handling of multi-bit binary addition by cascading multiple full adders.

Development of fuzzified neural network for enterprise bankruptcy risk estimation

The object of this study is the assessment of the level of enterprise bankruptcy risk. It is a critical component in assessing the financial condition of an enterprise, and also serves as an indicator that allows the management team to reduce potential risks and develop their own strategies to strengthen the financial condition of the enterprise. One of the most challenging aspects of bankruptcy forecasting is the complex financial situations of bankrupt companies. By accurately predicting the risk of bankruptcy, businesses can take preventive measures to mitigate financial difficulties and ensure long-term sustainability. Previous methods, such as Altman's Z-score, are not accurate enough, as presented in the study. The paper investigates a modern approach to bankruptcy prediction based on a neural network with complex neural elements, namely neural arithmetic logic units (NALUs) and a custom phasing layer. This layer can process complex raw numerical values, such as financial indicators relevant to the analysis of a company's bankruptcy. Compared to Altman's Z-score, the developed method demonstrates a better F1 score in bankruptcy classification (48 %). On the raw data, the neural network demonstrates an improvement in the F1 score by about 40 % compared to the classical multilayer perceptron (MLP) with linear layers and nonlinear activation functions. A modern replacement for ReLU called Mish was used, which achieves better generalization. It was also assumed that the addition of new neural elements, which provide the neural network with arithmetic capabilities, contributes to the performance of processing non-normalized input data. This work highlights the importance of using advanced neural network architectures to improve the accuracy and reliability of forecasting in financial risk assessment. Using the parameters presented in the study, managers of enterprises will be able to more accurately assess the risk of bankruptcy.

T-count and T-depth efficient fault-tolerant quantum arithmetic and logic unit

T-count and T-depth efficient fault-tolerant quantum arithmetic and logic unit