Arithmetic Logic Unit Operations Research Articles

High performance rapid single-flux-quantum bit-slice arithmetic logic unit

Two optimization technologies, namely, bypass and carry-control optimization, were demonstrated for enhancing the performance of a bit-slice Arithmetic Logic Unit (ALU) in 2n-bit Rapid Single-Flux-Quantum (RSFQ) microprocessors. These technologies can not only shorten the calculation time but also solve data hazards. Among them, the proposed bypass technology is applicable to any 2n-bit ALU, whether it is bit-serial, bit-slice or bit-parallel. The high performance bit-slice ALU was implemented using the 6 kA/cm2 Nb/AlOx/Nb junction fabrication process from Superconducting Electronics Facility of Shanghai Institute of Microsystem and Information Technology. It consists of 1693 Josephson junctions with an area of 2.46 × 0.81 mm2. All ALU operations of the MIPS32 instruction set are implemented, including two extended instructions, i.e., addition with carry (ADDC) and subtraction with borrow (SUBB). All the ALU operations were successfully obtained in SFQ testing based on OCTOPUX and the measured DC bias current margin can reach 86% - 104%. The ALU achieves a 100% utilization rate, regardless of carry/borrow read-after-write correlations between instructions.

50 GHz Operation of RSFQ Arithmetic Logic Unit Designed Using the Advanced Design Flow and the Dual RSFQ/ERSFQ Cell Library

Arithmetic Logic Unit (ALU) is an integral part of digital signal processing applications and computing systems. We used ALU, based on Kogge-Stone adder, as a reference circuit to experimentally validate the advanced design flow and the dual RSFQ/ERSFQ standard cell library. Using the advanced design flow, the ALU sub-blocks were optimized across multiple process corners using Monte-Carlo simulations incorporating statistical variations in the process parameters. The correct operation of ALU was verified in the digital HDL simulation using static timing analysis pre-fabrication. We designed the RSFQ 1-bit and 4-bit ALU using the standard cell library approach for MIT-LL 100 µA/µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fab node. For the ERSFQ 1-bit ALU, the bias current overhead for the feeding JTLs was designed to be 100% of the ERSFQ DUT bias current. The RSFQ 1-bit ALU, designed for low frequency functional testing, demonstrated greater than ±15% bias margins. We demonstrated successful operation of the RSFQ 4-bit ALU with greater than ±6% bias margins at 20 GHz, greater than ±5% bias margins at 40 GHz, and greater than ±4% bias margins at 50 GHz clock frequency with BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . The ERSFQ 1-bit ALU worked up to 30.72 GHz clock frequency with BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . In addition, we analyzed the model-to-hardware correlation for the INIT sub-block of the ALU. The simulations accounted for critical current density ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> ) and sheet resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R_s</i> ) process parameters. We noted the discrepancy in simulated and measured margins and studied that a 15% higher <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> in simulations results in better model-to-hardware correlation for the INIT sub-block.

Fin Field Effect Transistor with Active 4-Bit Arithmetic Operations in 22 nm Technology

A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits (ICs) fabrication industries. Because whenever device size comes down into narrow, designers facing many power density issues should be reduced by scaling threshold voltage and supply voltage. Initially, Complementary Metal Oxide Semiconductor (CMOS) technology supports power saving up to 32 nm gate length, but further scaling causes short severe channel effects such as threshold voltage swing, mobility degradation, and more leakage power (less than 32) at gate length. Hence, it directly affects the arithmetic logic unit (ALU), which suffers a significant power density of the scaled multi-core architecture. Therefore, it losses reliability features to get overheating and increased temperature. This paper presents a novel power minimization technique for active 4-bit ALU operations using Fin Field Effect Transistor (FinFET) at 22 nm technology. Based on this, a diode is directly connected to the load transistor, and it is active only at the saturation region as a function. Thereby, the access transistor can cutoff of the leakage current, and sleep transistors control the flow of leakage current corresponding to each instant ALU operation. The combination of transistors (access and sleep) reduces the leakage current from micro to nano-ampere. Further, the power minimization is achieved by connecting the number of transistors (6T and 10T) of the FinFET structure to ALU with 22 nm technology. For simulation concerns, a Tanner (T-Spice) with 22 nm technology implements the proposed design, which reduces threshold voltage swing, supply power, leakage current, gate length delay, etc. As a result, it is quite suitable for the ALU architecture of a high-speed multi-core processor.

Ultrafast all-optical ALU operation using a soliton control within the cascaded InGaAsP/InP microring circuits

A dark-bright soliton conversion is used to perform the two arithmetic logic unit operations namely adder and subtractor operations. The advantage of the system such as power stability, non-dispersion and the dark-bright soliton phase conversion control can be obtained. The input source into the circuit is the bright soliton pulse, with the pulse width of 35 ps, the peak power at 1.55 µm is 1 mW. By using the dark-bright soliton conversion pair, the generated logic bits can be controlled, and the secure bits can be achieved. The simulation results show the output signal with a minimum loss of only 0.1% with respect to a low input power of 1 mW, and ultra-fast response time of about 1 ps can be achieved. It gives the ultra-high bandwidth of more than 40 Gbits−1. The circuit composes six microring resonators made of InGaAsP/InP material with smaller ring radii of 1.5 µm, and the total physical scale of the circuit less than 100 µm2.

Logic Design of a 16-bit Bit-Slice Arithmetic Logic Unit for 32-/64-bit RSFQ Microprocessors

A 16-bit bit-slice arithmetic logic unit (ALU) is proposed for 32-/64-bit rapid single-flux-quantum microprocessors. It is based on a Ladner-Fischer adder. The ALU covers all of the ALU operations for MIPS32 instructions set. And each of the two 64-bit operands is divided into four slices of 16 bits each. The ALU uses synchronous concurrent-flow clocking and consists of 11 pipeline stages. The proposed ALU can be used for any 16n-bit processing.

4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessors

A 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for the MIPS32 instruction set. It processes bit-sliced 32-bit data that are divided into eight slices of 4 bits. The bit-slice approach simplifies the circuit structure and reduces the hardware cost. The ALU uses synchronous concurrent-flow clocking and consists of eight pipeline stages. It was implemented using the 1.0- $\mu\mbox{m} \mbox{Nb}/\mbox{AlO}_{x}/\mbox{Nb}$ nine-layer advanced process 2 (ADP2) with a critical current density of 10 kA/cm2, and fabricated by National Institute of Advanced Industrial Science and Technology (AIST). It consists of 3481 Josephson junctions with an area of $3.09 \times 1.66 \mbox{mm}^2$ . It achieved the target frequency of 50 GHz and a latency of 524 ps for a 32-bit operation, at the designed DC bias voltage of 2.5 mV, via precise control of interconnect delays and clock distribution. Furthermore, it achieved a throughput of $6.25 \times 10^9$ 32-bit operations per second. All the correct ALU operations with measured DC bias voltage margins of around 10% at 50 GHz were successfully obtained. The proposed ALU can be used for any $4n$ -bit processing.

8-Bit Asynchronous Sparse-Tree Superconductor RSFQ Arithmetic-Logic Unit With a Rich Set of Operations

This paper describes the design and testing of an 8-bit asynchronous wave-pipelined sparse-tree Rapid Single Flux Quantum (RSFQ) Arithmetic Logic Unit (ALU). Compared to previously developed RSFQ ALUs, this unit features an extensive set of 8 arithmetic and 12 logical operations. The execution of ALU operations consists of two steps. First, when necessary, one or both operands are inverted, and then operations are performed on these pre-processed data. Unlike the RSFQ Kogge-Stone-based designs, our parallel-prefix sparse-tree ALU has significantly reduced circuit complexity while maintaining robust operational margins at high frequency. An 8-bit ALU has been implemented with the International Superconductivity Technology Center (ISTEC) 10 kA/cm2 1.0 μm 9-metal ADP2.1 fabrication process as a joint effort between Stony Brook University, Yokohama National University, and Nagoya University. Using the CONNECT cell library and SFQ CAD tools developed at Nagoya and Yokohama, the Stony Brook team has developed a complete logical and physical design of the ALU chip. The 8-bit ALU core (without SFQ-to-dc and dc-to-SFQ converters) consists of 8832 Josephson junctions with an area of 7.2 mm2. Simulations show that the ALU can operate at the maximum rate of 42 GHz. It has the latency of 374 ps at a bias voltage of 2.5 mV. The chip was fabricated and tested at low frequency in 2012. Testing results showed malfunctioning of some gates but despite these shortcomings we still verified several ALU operations with the measured DC bias voltage margins of ±1.8%.

Low-Power Reconfigurable Processor Utilizing Variable Dual $V_{\rm DD}$

The dual-VDD technique has already been employed in reconfigurable processors to improve energy efficiency. In this brief, a variable dual-VDD method is proposed to reduce power consumption further through varying the level of the lower VDD (VDDL) according to the application on a processor. It finds out the optimum VDDL mainly based on the utilization times of all arithmetic logic unit operations by this application. In this estimation, the analysis of technology and architecture is highly required as well. Static timing analysis and power analysis were performed on the RPU, a reconfigurable processor designed in 65-nm CMOS technology. It is estimated that the proposed method can reduce the power of its reconfigurable array by 32% on average for the applications of GPS, MPEG2, H.264, and audio video coding standard (AVS). If VDDL is fixed at 0.6-0.75 V, the power reduction rate of the reconfigurable array will be 15% less on average. The area penalty of this method is less than 3%.

Interlock collapsing ALU's

A device capable of executing interlocked fixed point arithmetic logic unit (ALU) instructions in parallel with other instructions causing the execution interlock is presented. The device incorporates the design of a 3-1 ALU and can execute two's complement, unsigned binary, and binary logical operations. It is shown that status for ALU operations using a 3-1 ALU can be determined in a parallel fashion, resulting in the compliance of the proposed device with predetermined architectural behavior of single instruction execution. The device requires no more logic stages than does a 3-1 binary adder using a carry-save adder (CSA) followed by a carry-lookahead adder (CLA) design. Design considerations using a commonly available CMOS technology are also reported, indicating that the device will not increase the machine cycle of an implementation. It is suggested that the device can maintain full architectural compatibility.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>