Abstract
A 16-bit bit-slice arithmetic logic unit (ALU) is proposed for 32-/64-bit rapid single-flux-quantum microprocessors. It is based on a Ladner-Fischer adder. The ALU covers all of the ALU operations for MIPS32 instructions set. And each of the two 64-bit operands is divided into four slices of 16 bits each. The ALU uses synchronous concurrent-flow clocking and consists of 11 pipeline stages. The proposed ALU can be used for any 16n-bit processing.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
