Arithmetic Logic Unit Research Articles

Thermal Computing with Mechanical Transistors

AbstractMechanical computing has garnered significant interest as a supplement to traditional electronic computing, which often grapples with issues like high power consumption, security vulnerabilities, and susceptibility to extreme environmental conditions such as intense heat and radiation. Yet, most research in mechanical computing has been limited to the ad hoc design of simple logic gates and has not fully achieved the implementation of simple arithmetic computation within an electricity‐free framework. Additionally, progress in environmentally adaptive computing, crucial for decentralized intelligence, has also been slow. New ground is broken with the development of a mechanical transistor that synergizes a Kirigami thermomechanical sensor and a bistable actuator, enabling in‐memory computing for combinational and sequential logic. The design stands out by employing modular construction, symmetry breaking, and nonlinear materials, crafting logic gates, and memory units that respond to environmental stimuli through thermal delay. These transistors integrate design and material intelligence to establish nonvolatile memories, essential for logic‐in‐memory, and align thermal transport with mechanical deformation for environmental responsiveness. The mechanical transistor heralds a new age in mechanical computing, proving to be as versatile and vital as the electronic transistor has been in the era of modern computing.

Mathematical digital quantum computation by means of much more logical skills

We expand Deutsch’s algorithm for determining the mappings of a logical function using four orthogonal states. Using this, we propose a parallel computation for all of the combinations of values in variables of a logical function using sixteen orthogonal states. As an application of our algorithm, we demonstrate two typical arithmetic calculations in the binary system. We study an efficiency for operating a full adder/half adder by quantum-gated computing. The two typical arithmetic calculations are (1+1)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$(1+1)$$\\end{document} and (2+3)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$(2+3)$$\\end{document}. The typical arithmetic calculation (2+3)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$(2+3)$$\\end{document} is faster than that of its classical apparatus which would require 43=64\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$4^3=64$$\\end{document} steps when we introduce the full adder operation. Another typical arithmetic calculation (1+1)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$(1+1)$$\\end{document} is faster than that of its classical apparatus which would require 42=16\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$4^2=16$$\\end{document} steps when we introduce only the half adder operation.

Differential cognitive correlates in processing symbolic and situational mathematics

AbstractSymbolic and situational mathematics are the two major representations of mathematical knowledge. Although previous literature has studied the relationship between the two from the perspective of teaching practice, learning effectiveness and behavioural performance, there is still a lack of empirical psychological research on cognitive mechanisms to explore the psychological processes of the two. The current study investigated the relationship between symbolic and situational mathematics by determining the differences in cognitive correlates between the two in fourth‐grade children. Their symbolic and situational mathematics abilities were assessed using symbolic and situational enumeration tests under the same conditions. Several types of general cognitive abilities, language processing and academic achievements were also examined. Results showed that both situational and symbolic mathematics are crucial for mathematical achievement. Arithmetic computation is closely correlated with symbolic mathematics, whereas spatial processing and inductive reasoning ability are uniquely correlated with situational mathematics. The results suggest that situational and symbolic mathematics have separate cognitive correlates, which means the two are distinct in terms of psychological processing.

Microprocessor Design Using COPRAS Method

Introduction: A microprocessor is a computer and An important part of the structure, Without it, on your computer, Nothing can be done. it is a programmable device, It does some arithmetic on the input and logical operations and the desired output creates. In simple words, Microprocessor is on a chip It is a digital device Instructions from memory. Get them and decode them can run and give results. Fundamentals of Microprocessor. In a microprocessor machine language Take some steps that activate them, to the processor That's what it should do says Microprocessor instruction Three basics when implementing Doing things: Its addition, Subtraction, multiplication, division, and some logic functions Arithmetic and Logic Unit (ALU) makes use of. New Microprocessors are floating point Functions in numbers are doing In microprocessors The data in is from one location Can be moved to another location. It is a Program Counter (PC). Contains the registry, which Based on the value of the system address of the next instruction Stores, the microprocessor from place to place Jumps and makes decisions.Research significance: For microprocessor design, this Description Various semiconductors In device fabrication processes Made using some, Consequently in a chip carrier A drop in binding occurs. This chip carrier is then printed. Solder on the circuit board (PCB). done or in the socket is inserted. New microprocessor or microcontroller unit, To make the process flow logically Some general steps can be followed. These few steps make it even easier for small manageable tasks can be separated. A new microprocessor General steps for designing. A must-have in the new app is the determination of skills. required Data path to handle capabilities Set up. Machine code Instructional Design (ISA) Define. data path Create the necessary logic to control.Methodology: An analysis of the COPRAS method in this complex proportionality assessment (COPRAS) system in 1994 showed that the index values used to assess the Gavaskar, Kalkaska, and sarka introduced at this time increased and decreased. Alternatives: Poor life recycled products market, poor consumer perception of recycled products, poor supplier commitment, the poor success of curbside pickup. Evaluation Option: Finance Team, Engagement / Support, Infrastructure Team, Knowledge Team, Environment Team.Alternative: CISC is Intel 386, Intel 486, Pentium, EPIC is IA-64, DEC Alpha 21164. Evaluation preference: Feature size (micron), Supply voltage (V), Die size (mm2), DRAM bits/chip (m).Results: from the result, it is seen that CISC Intel 386 is got the first rank whereas DEC Alpha 21164 is having the lowest rank.

CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analysed using the Cadence Spectre.

Vector Accelerator Unit for Caravel

Caravel is an open-source project developed by Efabless for creating custom System-on-Chips (SoCs). It includes the design of a configurable chip, development tools, and documentation. The Caravel SoC includes a RISC-V with the Instruction Set Architecture RV32I. One of the key features of Caravel is its open-source nature. In this article, the Vector Accelerator Unit for the Caravel SoC template is presented to increase the RISC-V capabilities, allowing parallel data processing through 14 vector operations. The accelerator is based on 4 Arithmetic Logic Units connected directly to the RISC-V through Logic Analyzer port and the General-Purpose Input/Output (GPIO) port. The total area of this accelerator is less than 20% of the User Project Wrapper area allowing the user to implement their custom designs in 8.4256 mm.

Implementation of 64-Bit RISC Processor Using Vedic Multiplier

Abstract: In this project, 64 bit RISC processor designed with Vedic multiplier design. Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is mux- based full adders for building higher bit adders in an area and speed efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. A 64 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx Vivado 2018.3. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. Vedic Multiplier design is based on “Urdhva Triyakbhyam” which is among the 16 Vedic Sutras and MUX-Based Full Adders The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that savings in power in case of MAC and ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced in MAC and ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 64-bit Vedic processor is developed. This reduces the delay and saves area compared to conventional processor. Hence the improvement in speed of operation, and less area utilization are the key features of designed RISC processor.

Form perception is a cognitive correlate of the relation between subitizing ability and math performance.

"Subitizing" defines a phenomenon whereby approximately four items can be quickly and accurately processed. Studies have shown the close association between subitizing and math performance, however, the mechanism for the association remains unclear. The present study was conducted to investigate whether form perception assessed on a serial figure matching task is a potential non-numerical mechanism between subitizing ability and math performance. Three-hundred and seventy-three Chinese primary school students completed four kinds of dot comparison tasks, serial figure matching task, math performance tasks (including three arithmetic computation tasks and math word problem task), and other cognitive tasks as their general cognitive abilities were observed as covariates. A series of hierarchical regression analyses showed that after controlling for age, gender, nonverbal matrix reasoning, and visual tracking, subitizing comparison (subitizing vs. subitizing, subitizing vs. estimation) still contributed to simple addition or simple subtraction but not to complex subtraction ability or math word problem. After taking form perception as an additional control variable, the predictive power of different dot comparison conditions disappeared. A path model also showed that form perception fully mediates the relation between numerosity comparison (within and beyond the subitizing range) and arithmetic performance. These findings support the claim that form perception is a non-numerical cognitive correlate of the relation between subitizing ability and math performance (especially arithmetic computation).

Effects of green and urban environment exposure during classroom breaks in a video-based setting

AbstractNatural environments are beneficial for cognitive functioning and affect. Appraisals of such benefits can lead to the development of pro-environmental attitudes and behaviors in the long run. This study aimed to investigate the effects of an indirect exposure to a natural and urban environment during a short break in a school day, using a ‘green’ video depicting a walk through a lush forest and comparing it to an urban video portraying a walk through a busy city. We involved 91 fourth and fifth graders in a within-participants design. Results show that students decreased their performance in an arithmetic calculation task after watching the urban video, while no significant differences were observed before and after the exposure to the green environment. Students also reported experiencing more negative affect in relation to the exposure to the urban than the natural environment. Moreover, the students perceived the natural environment as more restorative than the urban environment. Taken together, our findings suggest that exposure to urban environments, in contrast to natural environments, may have negative effects on cognitive and affective functioning during school breaks. Educational implications suggest that when it is not possible to stay in a natural environment around the school, or there is no access to nature due to distance, videos of natural environments can be used during short breaks. They have potential to cognitively and affectively benefit students’ who may often be exposed to environmental stressors.

Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation area and transmission delay for arithmetic computation in DSP. In this study, we propose antilogarithmic converters with efficient error–area–delay products (eADPs) based on the fractional-bit compensation scheme. We propose three mathematical approximations—case 1, case 2, and case 3—to approximate the accurate antilogarithmic curve with different DSP requirements. The maximum percentage errors of conversion for case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with other methods reported in the literature. The proposed eADP-efficient antilogarithmic converters can achieve lower eADP and digitalized circuit implementation. The hardware implementation utilizes Verilog Hardware Description Language and the digital circuits are created via very-large-scale integration by the Taiwan Semiconductor Manufacturing Company with 0.18 µm CMOS technology. This proposed antilogarithmic converter can be efficiently applied in DSP.

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442 nW and 0.323 nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.

Enhancing ASIC chip performance through integrated algorithm optimization

As a crucial arithmetic logic unit, the multiplier plays a significant role in digital signal processing. However, multiplication operations often require a large number of calculations and logic gates, leading to increased circuit complexity and power consumption. To enhance the performance and efficiency of multipliers, this paper presents an optimization analysis based on the Wallace Tree and Booth algorithms. The Wallace Tree algorithm decomposes multiplication operations into multiple stages and employs both separate operations and bit-level parallelism to accelerate multiplication, achieving efficient parallel multiplication computations and reducing both latency and area complexity of multiplication. On the other hand, the Booth algorithm is an optimization method for signed binary multiplication. By introducing the concept of Booth encoding, it transforms signed multiplication into unsigned multiplication, thereby reducing the number of multiplication operations. This paper analyses the application and research progress of the Wallace Tree and Booth algorithms in the field of multiplier optimization to improve computational speed and reduce power consumption of multipliers.

Enhancing multiplication efficiency: Harnessing Booth algorithm and Wallace tree synergy for 32-bit signed multipliers

This paper focuses on exploring performance optimization strategies for 32-bit signed multipliers in the realm of digital computation. The ingenious combination of the Booth algorithm and the Wallace tree takes center stage as the core of this research. Through a thorough analysis of this combined technique, the paper unveils its multifaceted advantages in multiplication operations. The unique contribution of the Booth algorithm is elaborately discussed, which involves streamlining the multiplication process by reducing the number of addition operations. Subsequently, the exceptional performance of the Wallace tree in accelerating the merging of partial products is highlighted. Through the synergistic interplay of these two techniques, the efficiency of multiplication operations is significantly enhanced, particularly suited for domains necessitating high-speed arithmetic computations, such as graphics processing and digital signal processing. The paper delves further into the significance of optimizing resource utilization, particularly in the field of integrated circuit design. By minimizing addition operations and optimizing parallel processing, the complexity of hardware implementation is reduced, leading to a notable decrease in resource requirements. This advantage proves invaluable in modern integrated circuit design, aiding designers in striking an optimal balance between spatial efficiency and power consumption.

A new nano-design of configurable logic module based on coplanar reversible adder and modified Fredkin gates using quantum technology

Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications.

Design a 5-stage pipeline RISC-V CPU and optimise its ALU

The RISC-V instruction set has advanced and expanded significantly in recent years. It is an open instruction set architecture (ISA) based on the concept of Reduced Instruction Set Computing (RISC). This article uses Verilog to design a 5-stage pipeline CPU based on RISC-V architecture in Vivado 2022.2. The CPU can execute 38 instructions and optimises its arithmetic logic unit (ALU) by optimising adders, shifters, and multipliers. Next, write a testbench in the simulation software to verify the functionality of the CPU. RTL diagrams and reports are then generated to verify the design structure and evaluate resource allocation. Finally, the CPU successfully executes the instruction and obtains the correct operation result, and the occupation of LUT resources in the shifter part is reduced. This work serves as an important reference for system-on-chip (SoC) and computer design in general. It not only highlights the potential of the RISC-V architecture but also demonstrates the success of optimisation efforts. This paves the way for more powerful and efficient computing systems.

Use of information redundancy to increase the reliability of devices for storing, processing and transmitting information

In modern information transmission systems, a special place is occupied by telecommunication systems (TS), which include digital data transmission systems (DSTS) containing specialized computers (SEVMs). The systems under consideration must ensure fast and reliable transmission of discrete data over communication lines. In this case, the loss of even one transmitted character is unacceptable; therefore, the main indicator of the reliability of a computer is the probability of failure-free operation. To increase the probability of failure-free operation of a storage device (MS), corrective codes and duplication are used, and to increase the probability of failure-free operation of the arithmetic-logical unit (ALU) of a computer, majority redundancy is used. The disadvantage of the majority method is the high hardware costs for redundancy, which reduces the efficiency of its use. The disadvantages of using correction codes include: as a rule, they are used for separate redundancy (detection and correction of errors that occur in storage devices; majority redundancy is used to detect and correct errors in the ALU); not all arithmetic and logical operations can be controlled based on existing correcting codes; a sharp increase in hardware costs when using algebraic linear codes to detect and correct multiple errors. Detection of errors in the ALU of a computer processor can be achieved on the basis of duplication in a loaded mode with replacement, however, this is associated with solving the main problem of computer duplication: - selection of monitoring tools for determining a failed channel (detection of errors in storage and information processing devices). The purpose of the research is to develop a scientific and methodological apparatus for computer backup using the duplication method with error detection in backup channels based on the use of an algebraic linear code, which makes it possible to detect errors not only in storage devices, but also adapted for detecting errors when performing arithmetic and logical operations. Results. An analysis of operation and selection of reliability indicators for specialized computers (SEVMs) of telecommunication systems was carried out. Requirements for computer backup methods are formulated. A comparative assessment of the detecting ability and hardware costs was carried out when implementing the majority redundancy method, the duplication method and the use of correcting codes. The expediency of using the duplication method is substantiated to increase the probability of failure-free operation and survivability of self-healing digital computers, using algebraic linear codes to determine the faulty channel, which allows to significantly reduce hardware costs for constructing monitoring equipment and use 10-30% of backup equipment for these purposes. It is proposed to use an algebraic linear code, in which, unlike well-known codes, the values of the check bits correspond to the direct and inverse values of the information bits, which makes it possible to detect errors when reading information from the inverse outputs of the memory, correct single errors, detect double errors and control the logical inversion operation , necessary to represent a negative number in two's complement code, which makes it possible to adapt the code to control arithmetic and logical operations of the computer processor. An assessment was made of the probability of failure-free operation of a duplicated computer, with its general redundancy, with detection and correction of single errors in the backup memory channels and detection of errors in the backup channels of the processor ALU based on the proposed code, and an assessment of the probability of failure-free operation of the computer, with its separate redundancy, with error detection in the backup channels of the duplicated memory based on the Hamming code and error correction in the backup channels of the processor ALU based on the majority method. A comparative assessment of the probabilities of failure-free operation allows us to conclude that the general redundancy of the computer based on the proposed code, in comparison with the separate redundancy of the memory and ALU of the computer processor, allows for a gain in the probability of failure-free operation of the computer and its functional devices throughout the entire period of operation. The practical significance lies in the fact that the proposed scientific and methodological apparatus provides: reduction of hardware costs for identifying a faulty channel when organizing duplication; detection of errors in the memory and ALU of the computer processor with time costs not exceeding the time of error detection when using standard methods of monitoring the computer system.

Fast Multilevel Mental Stress Identification From Bispectrum-Based Heart Rate Variability Feature

Fast and accurate identification of mental stress is critical to reducing its risk to human health and the related consequences in industry. This study proposed a bispectrum-based feature to improve the accuracy and reduce the latency of multi-level mental stress identification from heart rate variability (HRV). The performance was evaluated by two stress induction protocols, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i.e.</i> , Stroop color-word interference test (SCIT) and mental arithmetic calculation (MAC), and the results demonstrated that the bispectrum-based methods significantly outperformed traditional HRV features with windows as short as 15 s. The high-order components found by an established nonlinear test, and the strong feature correlations detected between short and long windows, further validated the effectiveness and the feasibility of the proposed methods on mental stress identification from super-short windows. The results had the potential to promote the applications of HRV-based mental stress management across industries with the Internet of Medical Things (IoMT) devices.

A Review of Contact Models’ Properties for Discrete Element Simulation in Agricultural Engineering

In agricultural engineering, the discrete element simulation of the operational structure, object of movement, and force has become a standard method of modern agricultural equipment design. The selection and development of an appropriate contact model are critical factors affecting the accuracy of the process of the simulation calculation of the movement and force. Understanding how to choose or establish suitable contact models according to different research fields, objects, and purposes has become the focus of present research. This paper gives an overview of contact models for discrete element simulation, summarizes and analyzes the simulation calculation basis of different contact models, and focuses on the application status and scenarios of different models at this stage. It analyzes and summarizes the selection basis and application fields of contact models. The next direction in the development of discrete element simulation contact models should be the hybrid application of multicontact models and the precise development of specialized contact models. It is necessary to establish a standardized parameter-calibration process for different contact models to guarantee the accuracy of the models, to improve the application of computer arithmetic, and to establish an efficient and accurate simulation contact model selection and application in the field of agricultural engineering. Efficient and accurate simulation contact model selection, design theory, and calculation processes will improve the efficiency of modern agricultural machinery design.

The Mechanism of The Arithmetic Logic Unit

The Arithmetic Logic Unit is widely used in electrical components nowadays such as the CPU in computers. The traditional research is based on the theory of a combination of multiple logic units, the results are not performed intuitional. This paper provides an introduction to the Arithmetic Logic Unit and its mechanisms, which consist of multiple logic gates to perform binary operations and send commands to the computer. The article discusses binary operations using logic gates, starting from the simplest one-bit half-adder to the more complex four-bit ALU, encompassing functions like addition, subtraction, division, and multiplication. The simulation module is used to justify the mechanism of the ALU. This research provides a new method in the process of developing the ALU, may largely increases the productivity. The approach may be used in the research and development of computer performance, providing visual, instant feedback and reducing the cost.

Coupled Ferroelectric-Photonic Memory in a Retinomorphic Hardware for In-Sensor Computing.

The development of all-in-one devices for artificial visual systems offers an attractive solution in terms of energy efficiency and real-time processing speed. In recent years, the proliferation of smart sensors in the growth of Internet-of-Things (IoT) has led to the increasing importance of in-sensor computing technology, which places computational power at the edge of the data-flow architecture. In this study, a prototype visual sensor inspired by the human retina is proposed, which integrates ferroelectricity and photosensitivity in two-dimensional (2D) α-In2Se3 material. This device mimics the functions of photoreceptors and amacrine cells in the retina, performing optical reception and memory computation functions through the use of electrical switching polarization in the channel. The gate-tunable linearity of excitatory and inhibitory functions in photon-induced short-term plasticity enables to encode and classify 12000 images in the Mixed National Institute of Standards and Technology (MNIST) dataset with remarkable accuracy, achieving ≈94%. Additionally, in-sensor convolution image processing through a network of phototransistors, with five convolutional kernels electrically pre-programmed into the transistors is demonstrated. The convoluted photocurrent matrices undergo straightforward arithmetic calculations to produce edge and feature-enhanced scenarios. The findings demonstrate the potential of ferroelectric α-In2Se3 for highly compact and efficient retinomorphic hardware implementation, regardless of ambipolar transport in the channel.