Arithmetic Algorithms Research Articles

Pipeline Architecture for N=K*2L Bit Modular ALU: Case study between current generation computing and Vedic computing

This paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. These algorithm have been evaluated with better performance, area and speed. The literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. The proposition is on realizing N-bit using ‘2L’ as base modules using ‘K’ modules in pipelining. The authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU. The authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

Pipeline Architecture for N=K*2L Bit Modular ALU: Case study between current generation computing and Vedic computing

This paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. These algorithm have been evaluated with better performance, area and speed. The literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. The proposition is on realizing N-bit using ‘2L’ as base modules using ‘K’ modules in pipelining. The authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU. The authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

Validation of Differentially Expressed Immune Biomarkers in Latent and Active Tuberculosis by Real-Time PCR.

Tuberculosis (TB) remains a major global threat and diagnosis of active TB ((ATB) both extra-pulmonary (EPTB), pulmonary (PTB)) and latent TB (LTBI) infection remains challenging, particularly in high-burden countries which still rely heavily on conventional methods. Although molecular diagnostic methods are available, e.g., Cepheid GeneXpert, they are not universally available in all high TB burden countries. There is intense focus on immune biomarkers for use in TB diagnosis, which could provide alternative low-cost, rapid diagnostic solutions. In our previous gene expression studies, we identified peripheral blood leukocyte (PBL) mRNA biomarkers in a non-human primate TB aerosol-challenge model. Here, we describe a study to further validate select mRNA biomarkers from this prior study in new cohorts of patients and controls, as a prerequisite for further development. Whole blood mRNA was purified from ATB patients recruited in the UK and India, LTBI and two groups of controls from the UK (i) a low TB incidence region (CNTRLA) and (ii) individuals variably-domiciled in the UK and Asia ((CNTRLB), the latter TB high incidence regions). Seventy-two mRNA biomarker gene targets were analyzed by qPCR using the Roche Lightcycler 480 qPCR platform and data analyzed using GeneSpring™ 14.9 bioinformatics software. Differential expression of fifty-three biomarkers was confirmed between MTB infected, LTBI groups and controls, seventeen of which were significant using analysis of variance (ANOVA): CALCOCO2, CD52, GBP1, GBP2, GBP5, HLA-B, IFIT3, IFITM3, IRF1, LOC400759 (GBP1P1), NCF1C, PF4V1, SAMD9L, S100A11, TAF10, TAPBP, and TRIM25. These were analyzed using receiver operating characteristic (ROC) curve analysis. Single biomarkers and biomarker combinations were further assessed using simple arithmetic algorithms. Minimal combination biomarker panels were delineated for primary diagnosis of ATB (both PTB and EPTB), LTBI and identifying LTBI individuals at high risk of progression which showed good performance characteristics. These were assessed for suitability for progression against the standards for new TB diagnostic tests delineated in the published World Health Organization (WHO) technology product profiles (TPPs).

Adversarial Hardware With Functional and Topological Camouflage

The lately attack on the Qualcomm’s Snapdragon chip reminds us security risks related to digital arithmetic circuits. Most system designers neglect the employed computer arithmetic algorithms or their implementation details. Arithmetic circuits are therefore usually used as “black box” units that are instantiated by third-party intellectual-property core or electronic design-automation tool vendors. In this brief, we propose the first most-significant digit-first arithmetic-based hardware Trojan attack by addressing the questions of where to insert and with what . First, we demonstrate how functional camouflage is achieved. Certain arithmetic modules can be quietly replaced with functionally equivalent ones, which we term functionally camouflaged Trojans. Next, we introduce a topologically camouflaged Trojan by employing graph-centrality analysis on rare behaviours in the circuit. The proposed approach is applicable to any digital computing scenarios. Experimental results on a financial computing system demonstrate that completely inaccurate numeric results are yielded, along with an up-to 91.6% numerical error tested.

Development of a Mathematical Model for Simulating the Self-Heating Behavior of Moist Coal

ABSTRACT Oxidation of fresh coal in the low-temperature region involves a series of processes. This starts with the adsorption of oxygen on the available fresh coal pore surfaces and continues with the high rate oxidation of coal. A new reaction kinetics expression has been proposed covering the whole low-temperature region of coal self-heating. Also, a comprehensive evaporation/drying model has been developed and validated to express the moisture removal rate of coal during self-heating. By combining these two improvements for describing the self-heating process a more robust mathematical model has been developed. Calculations have been carried out using an arbitrary-precision arithmetic algorithm in MATLAB. The model predictions have been validated by the actual moist coal self-heating behavior in an adiabatic oven.

Application of Deep Learning for Speckle Removal in GOCI Chlorophyll-a Concentration Images (2012–2017)

The detection and removal of erroneous pixels is a critical pre-processing step in producing chlorophyll-a (chl-a) concentration values to adequately understand the bio-physical oceanic process using optical satellite data. Geostationary Ocean Color Imager (GOCI) chl-a images revealed that numerous speckle noises with enormously high and low values were randomly scattered throughout the seas around the Korean Peninsula as well as in the Northwest Pacific. Most of the previous methods used to remove abnormal chl-a concentrations have focused on inhomogeneity in spatial features, which still frequently produce problematic values. Herein, a scheme was developed to detect and eliminate chl-a speckles as well as erroneous pixels near the boundary of clouds; for the purpose, a deep neural network (DNN) algorithm was applied to a large-sized GOCI database from the 6-year period of 2012–2017. The input data of the proposed DNN model were composed of the GOCI level-2 remote-sensing reflectance of each band, chl-a concentration image, median filtered, and monthly climatology chl-a image. The quality of the individual images as well as the monthly composites of chl-a data was improved remarkably after the DNN speckle-removal procedure. The quantitative analyses showed that the DNN algorithm achieved high classification accuracy with regard to the detection of error pixels with both very high and very low chl-a values, and better performance compared to the general arithmetic algorithms of the median filter and threshold scheme. This implies that the implemented method can be useful for investigating not only the short-term variations based on hourly chl-a data but also long-term variabilities with composite products of the GOCI chl-a concentration over the span of a decade.

Fast Discrete Wavelet Transformation Using FPGAs and Distributed Arithmetic

ABSTRACT The discrete wavelet transform has gained the reputation of being a very effective signal analysis tool for many practical applications. However, due to its computation-intensive nature, current implementations of the transform fall short of meeting real-time processing requirements of most applications. This paper describes a parallel implementation of the discrete wavelet transform and its inverse using high-density field programmable logic devices (FPGAs). The implementation exploits the lookup table-based architecture of Virtex FPGAs, by reformulating the wavelet computation in accordance with the distributed arithmetic algorithm. Performance results show that the distributed arithmetic formulation results in a considerable performance gain compared with the conventional arithmetic formulation of the wavelet computation. Finally, we show that the FPGA implementation outperforms alternative software implementations of the discrete wavelet transform.

A quantum circuit simulator and its applications on Sunway TaihuLight supercomputer

Classical simulation of quantum computation is vital for verifying quantum devices and assessing quantum algorithms. We present a new quantum circuit simulator developed on the Sunway TaihuLight supercomputer. Compared with other simulators, the present one is distinguished in two aspects. First, our simulator is more versatile. The simulator consists of three mutually independent parts to compute the full, partial and single amplitudes of a quantum state with different methods. It has the function of emulating the effect of noise and support more kinds of quantum operations. Second, our simulator is of high efficiency. The simulator is designed in a two-level parallel structure to be implemented efficiently on the distributed many-core Sunway TaihuLight supercomputer. Random quantum circuits can be simulated with 40, 75 and 200 qubits on the full, partial and single amplitude, respectively. As illustrative applications of the simulator, we present a quantum fast Poisson solver and an algorithm for quantum arithmetic of evaluating transcendental functions. Our simulator is expected to have broader applications in developing quantum algorithms in various fields.

Use Two Hybrid SCA-AOA and Fuzzy SCA-AOA Algorithms in Information Security

This research suggests the improving Sine Cosine algorithm and Arithmetic optimization algorithm (SCA-AOA), and the application in two directions: First, in special functions (N-P hard) problems; second, in code analysis and decryption for the method of encryption substitution of simple cipher. The proposed algorithm mathematically simulates the behavior of SCA and Arithmetic algorithm behavior in Mathematical. The measure of SCA-AOA has been measured on a set of test functions to know the power of its performance and efficiency, and verify and compare it with SCA and AOA, each one alone. The numerical results have proved that the proposed algorithm (SCA-AOA) is able to present excellent results as compared with SCA-AOA itself. The applied results have proved that the proposed algorithm is able to analyze and break code. It could also avoid the falling the local solution and reaching to the global optimum resolutions in majority of functions that have been applied on. The adoptive Fuzzy SCA-AOA has been proposed and used in analyzing cipher text and breaking the code by merging the proposed algorithm SCA-AOA with properties of fuzzy logic. Moreover, the simple encoding method is explained and used to encode the proposed text. The method of masking by images is explained and used to hide text. The standards are used to measure the image resolution and find the image resolution. The encrypted text was analyzed and returned to the explicit text using the proposed method, SCA-AOA and Fuzzy SCA-AOA both separately, and the code for the encryption was broken by the proposed method.

Taxonomic Studies on Some Members of the Genus <i>Abutilon</i> Mill. (Malvaceae)

The relationship between six Abutilon species was examined using different taxonomic investigation tools. The investigation was carried out using morphological and numerical studies. Fresh materials of Abutilon species were collected from different localities in Saudi Arabia during 2018 and 2019. Numerical analysis was based on the Principle Coordinates, the Principle Component and the Unweighted Pair Group Method with Arithmetic Algorithm Clustering. The results indicated that there were significant differences based on the morphological characters especially in the leaves, fruits and flowers features. Morphometric studies revealed that the six species of Abutilon clearly separated in all different analysis.

Design And Implementation Of Iterative Dct Using Concurrent Loading For Image Encoding

Discrete Cosine Transform (DCT) is the most widely used transformforsignal compression in many image and video processing applications. Spatial signals are transformed to frequency domain in which the signal is broken down into different frequency components Through DCT. DCT is generally used for image compression but also for noise reduction in images. But various digital architectures developed for computing DCT for images require large computations resulting in a complex and costly design. So a design of an advanced model of parallel DCT with iterative looping structureis proposed to process images. The benefit of such 8-point iterative DCT architecture is that it improves the resolution of the input image thereby utilizing low power principle and finally transforms the image data with reduced errors. The iterative DCT used in this system results in reduced processing time. The digital architecture used for the image processing follows distributed arithmetic algorithm. As a result, the proposed system achieves an area reduction of 47% and an energy reduction of 65.55%.

Efficient Architecture for the Realization of 2-D Adaptive FIR Filter Using Distributed Arithmetic

This paper presents an efficient architecture for two-dimensional (2-D) adaptive FIR filter architecture using the distributed arithmetic (DA) algorithm. DA-based filter architectures essentially require look-up tables (LUT). In the proposed filter architecture, RAM- or ROM-based LUT is replaced by adders- and logic gates-based structure that generates the LUT value corresponding to the input. Therefore, the MAC unit requires fewer logic gates and adders in DA-based realization. In addition, the memory sharing concept in architecture reduces the delay elements. Moreover, the complexity of the LUT hardware of higher-order filters is reduced by parallelly dividing the internal MAC block for the DA decomposition which offers a higher degree of modularity and parallelism in the proposed architecture. Further, 2-D delayed LMS algorithm is used for the updation of the filter coefficient weights. Furthermore, two-stage pipelining is used to reduce the critical path of the architecture and it also makes critical path delay independent of the order of the filter. ASIC synthesis results reveal the advantages of the proposed structure by reducing the area, power, ADP and EDP by 54%, 48.19%, 55% and 49%, respectively, as compared with the existing architecture for filter size 8 × 8.

RNS Bases in Computer Architecture for DNA Sequence Application

In this paper we present an RNS algorithm and architecture implementation of gene sequence applications based on an existing RNS arithmetic algorithm. Investigation was made on RNS application and its inherent arithmetic advantages; data conversion algorithm from Decimal/Binary to RNS; the forward conversion; Conversion from RNS to Binary/Decimal; the reverse conversion using the Chinese remainder theorem CRT, conversion from RNS to mixed radix form with capability for effective computation performance, and analysis of Smith Waterman Algorithm based on DNA sequence computing. Its limitations and open issues for future research were highlighted.

Comparison of Entropy and Dictionary Based Text Compression in English, German, French, Italian, Czech, Hungarian, Finnish, and Croatian

The rapid growth in the amount of data in the digital world leads to the need for data compression, and so forth, reducing the number of bits needed to represent a text file, an image, audio, or video content. Compressing data saves storage capacity and speeds up data transmission. In this paper, we focus on the text compression and provide a comparison of algorithms (in particular, entropy-based arithmetic and dictionary-based Lempel–Ziv–Welch (LZW) methods) for text compression in different languages (Croatian, Finnish, Hungarian, Czech, Italian, French, German, and English). The main goal is to answer a question: ”How does the language of a text affect the compression ratio?” The results indicated that the compression ratio is affected by the size of the language alphabet, and size or type of the text. For example, The European Green Deal was compressed by 75.79%, 76.17%, 77.33%, 76.84%, 73.25%, 74.63%, 75.14%, and 74.51% using the LZW algorithm, and by 72.54%, 71.47%, 72.87%, 73.43%, 69.62%, 69.94%, 72.42% and 72% using the arithmetic algorithm for the English, German, French, Italian, Czech, Hungarian, Finnish, and Croatian versions, respectively.

On the risks of using double precision in numerical simulations of spatio-temporal chaos

Due to the butterfly-effect, computer-generated chaotic simulations often deviate exponentially from the true solution, so that it is very hard to obtain a reliable simulation of chaos in a long-duration time. In this paper, a new strategy of the so-called Clean Numerical Simulation (CNS) in physical space is proposed for spatio-temporal chaos, which is computationally much more efficient than its predecessor (in spectral space). The strategy of the CNS is to reduce both of the truncation and round-off errors to a specified level by implementing high-order algorithms in multiple-precision arithmetic (with sufficient significant digits for all variables and parameters) so as to guarantee that numerical noise is below such a critical level in a temporal interval t∈[0,Tc] that corresponding numerical simulation remains reliable over the whole interval. Without loss of generality, the complex Ginzburg-Landau equation (CGLE) is used to illustrate its validity. As a result, a reliable long-duration numerical simulation of the CGLE is achieved in the whole spatial domain over a long interval of time t∈[0,3000], which is used as a reliable benchmark solution to investigate the influence of numerical noise by comparing it with the corresponding ones given by the 4th-order Runge-Kutta method in double precision (RKwD). Our results demonstrate that the use of double precision in simulations of chaos might lead to huge errors in the prediction of spatio-temporal trajectories and in statistics, not only quantitatively but also qualitatively, particularly in a long interval of time.

A Why3 proof of GMP algorithms

Large-integer arithmetic algorithms are used in contexts where both their performance and their correctness are critical, such as cryptographic software. The fastest algorithms are complex enough that formally verifying them is desirable but challenging. We have formally verified a comprehensive arbitrary-precision integer arithmetic library that implements many state-of-the-art algorithms from the GMP library. The algorithms we have verified include addition, subtraction, Toom-Cook multiplication, division and square root. We use the Why3 platform to perform the proof semi-automatically. We obtain an efficient and formally verified C library of low-level functions on arbitrary-precision natural integers. This verification covers the functional correctness of the algorithms, as well as the memory safety and absence of arithmetic overflows of their C implementation. Using detailed pseudocode, we present the algorithms that we verified and outline their proofs.

Electronic Abacus (e-Abacus) using FPGA Altera DE2 Board

The development of electronic abacus using Altera DE2 115, is to integrate the use of abacus along with electronic devices which offer better visualisation of the abacus operations. The main focus of this technology is to assist the primary school students in validating a fundamental arithmetic operation. The electronic abacus is developed by integrating an abacus, abacus decoder module and field programming gate array (FPGA) based processor. DE2 115 is chosen as the development module and very high-speed integrated circuit hardware description language (VHDL) as a main programming language. The arithmetic algorithm developed for the electronic abacus is limited to the computational of whole numbers only, involving the basic arithmetic operation of additional, subtraction, multiplication and division. This electronic abacus comes with two operational modes, display and arithmetic mode. In the display mode, the abacus beads position at column one until column seven is displayed as numerical representation on the liquid crystal display (LCD) screen. A computation of arithmetic operations with less than three operators is available in the arithmetic mode with the capability of displaying the negative numerical and infinite value. From the simulation conducted in Quartus II, the implementation of the algorithm in FPGA utilise 4% from the total logical element allowed and consume approximately 143.4 mW of power. As a conclusion, this enhanced ancient apparatus hopefully will contribute to the development of more lively and interesting teaching approach.

Memory Efficient High Speed Systolic Array Architecture Design with Multiplexed Distributed Arithmetic for 2D DTCWT Computation on FPGA

This paper presents customized Systolic Array Architecture (SAA) design of Dual Tree Complex Wavelet (DTCWT) sub band computation based on multiplexed Distributive Arithmetic Algorithm (DAA). The proposed architecture is memory efficient and operates at frequencies greater than 300 MHz in decomposing 256 x 256 input images. Three architectures such as reduced order structure, multiplexed DA structure and zero pad structure are designed and evaluated for its performances for DTCWT computation minimizing arithmetic operations with improved latency. The proposed design is modeled in Verilog HDL and is implemented on Spartan-6 and Virtex-5 FPGA considering Xilinx ISE FPGA design flow. The latency of proposed architectures is evaluated to be 15 clock cycles and throughput is estimated to be 4 outputs for every 5 clock cycles. The SAA architecture occupies less than 12% of FPGA resources and consumes less than 10 mW of power on FPGA platform.

A New Algorithm for Fast Generalized DFTs

We give an new arithmetic algorithm to compute the generalized Discrete Fourier Transform (DFT) over finite groups G . The new algorithm uses O (∣ G ∣ ω /2 + o (1) ) operations to compute the generalized DFT over finite groups of Lie type, including the linear, orthogonal, and symplectic families and their variants, as well as all finite simple groups of Lie type. Here ω is the exponent of matrix multiplication, so the exponent ω/2 is optimal if ω = 2. Previously, “exponent one” algorithms were known for supersolvable groups and the symmetric and alternating groups. No exponent one algorithms were known, even under the assumption ω = 2, for families of linear groups of fixed dimension, and indeed the previous best-known algorithm for SL 2 (F q ) had exponent 4/3 despite being the focus of significant effort. We unconditionally achieve exponent at most 1.19 for this group and exponent one if ω = 2. Our algorithm also yields an improved exponent for computing the generalized DFT over general finite groups G , which beats the longstanding previous best upper bound for any ω. In particular, assuming ω = 2, we achieve exponent √ 2, while the previous best was 3/2.

Design and Implementation of LMS Adaptive FIR Filter Based on OBC Distributed Arithmetic Algorithm with MCSLA

Design and Implementation of LMS Adaptive FIR Filter Based on OBC Distributed Arithmetic Algorithm with MCSLA