Power-delay-area Product Research Articles

A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements

With the continuous reduction of feature size of transistors, single-event triple-node-upsets (TNUs) induced by the striking of radiation particles in nano-scale CMOS circuits have emerged as a significant reliability concern. To address the shortcomings of existing radiation-hardened designs, including low reliability and high overhead, this paper proposes a cost-effective and highly robust TNU self-recovery latch design called DOCTRL. The proposed DOCTRL latch primarily consists of six dual-output C-elements (DOCs) and two clocked DOCs. By utilizing DOCs with two independent outputs, the proposed DOCTRL latch achieves a smaller area overhead. In addition, a four-level circular interlock matrix connection is designed to recover all possible TNUs within the proposed DOCTRL latch. Meanwhile, the latch also incorporates clock gating technology and a high-speed path to minimize power consumption and delay penalties. Simulation results indicate that the proposed DOCTRL reduces area by an average of 32.43 %, power consumption by 46.84 %, delay by 14.43 %, and area-power-delay product (APDP) by 69.55 %, compared to the five typical TNU self-recovery latches (SCLCRL, TNUSH, LCTNUCR, ADTRL, TSRL). Furthermore, detailed process, voltage, temperature (PVT), and Monte Carlo simulations verify the robustness of the proposed DOCTRL latch.

Realization of a high-efficient GDI-based 4:2 compressor for sum of absolute difference detection in image and signal processing

A new 4:2 approximate compressor is designed based on gate diffusion input (GDI), which has 14 transistors and only 6 errors in its outputs. The integration of the GDI with the dynamic threshold (DT) overcomes the body effect by the selection of carbon nanotube field-effect transistors (CNTFET) technology. By embedding the proposed compressor in the 8-bit sum of absolute difference (SAD) system, an area of 284.6 µm2 is occupied and a reliable system for difference detection between two images and electrocardiogram (ECG) results. Considering the fair conditions of comparison, the proposed circuit has significant performance in terms of circuitry parameters such as power, delay, and figure of merits (FoMs). In terms of power-delay-product (PDP) and power-delay-area-product (PDAP) the proposed cell shows a saving of 27 % and 47 %, respectively. A 40 % improvement in terms of a FoM containing PDP and power signal-to-noise ratio (PSNR) compared to the closest competitor qualifies the proposed circuit over the other counterparts. The proposed cell has a high performance under the difference detection in images and ECGs.

A highly reliable and low-overhead quadruple-node-upset tolerant latch design

With the advancement of semiconductor technology and the continual reduction in the feature size of transistors within integrated circuits (ICs), ICs are becoming more and more vulnerable to soft errors induced by energetic particles in harsh radiation environments. To mitigate the impact of soft error on ICs. This paper proposes a quadruple-node-upset tolerant latch (LCQNUT), which consists of two parts: a storage module and a three-stage interception module. The storage module is composed of 12 dual-input inverters. The three-stage interception module is composed of 6 dual-input C-elements (CEs). Based on the CEs and dual-input inverters' blocking capability, the proposed LCQNUT latch can efficiently tolerate the simultaneous upset of any four internal node combinations. Simulation results indicate the proposed LCQNUT latch has the smallest power consumption, area overhead, and area-power-delay product (APDP) compared to the latches with the same soft tolerance ability (D-LATCH, HS-QNU, QNUTL). It has moderate sensitivity to process, voltage, and temperature (PVT).

DAFA: Dynamic approximate full adders for high area and energy efficiency

As the number of transistors on a chip surface increases, power consumption becomes more and more a serious concern. A promising solution to bridge the gap between resource-constrained gadgets and computation-intensive applications could be the approximate computing paradigm. This paper presents four efficient approximate full adder cells based on dynamic logic and carbon nanotube field-effect transistors (CNFETs). To the best of our knowledge, dynamic logic has never been deployed in the design of approximate full adders before. Comprehensive simulations and analyses are conducted to study the efficacy of the new circuits. Simulation results indicate remarkable improvements compared to state-of-the-art circuits. For instance, at 0.9 V power supply, our final proposed design improves the power-delay-area product (PDAP) metric by at least 63% compared to its peers. Moreover, the applicability of the proposed adders in the image sharpening application is examined by measuring peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) using the MATLAB tool. The proposed designs have also a reasonable performance in this regard.

An ultra low‐power double‐node‐upsets hardened latch design

AbstractIn this paper, a novel low‐cost, double‐node upset (DNU) tolerant latch aiming at nourishing the lack of these devices in the state of the art was presented, especially featuring high reliability while maintaining a low‐cost profile. The proposed latch is based on a low‐cost single event double‐node upset tolerant latch and also provides self‐recoverability against double‐node‐upsets. The latch uses clock‐controlled DICE (Dual‐interlocked storage cell) cell and CE(C‐Elements) cell to tolerate double‐node‐upsets fully. The Simulation waveforms and analysis results show that the proposed latch can maintain the correct output in any case of DNU. In addition, under the premise of high radiation tolerance, the minimum improvement of the area‐power‐delay product (APDP) of the proposed low‐power double‐node‐upsets hardened latch (LPDHL) is 16.60%, compared with the latest DNU tolerant latch on the literature.

Low cost and high performance double‐node upset resilient latch for low orbit space applications

SummaryThis paper proposes a double‐node upset complete resilient (DNUCR) latch to meet the requirements of low orbit space applications for high robustness, cost‐effectiveness, and high performance. With the help of its interlocked loops with multiple feedbacks consisting of C‐elements (CE), input splitting CEs, 1P‐2N and 2P‐1N elements, and inverters, the proposed DNUCR latch preserves the original data even after the radiation incident. Error injection simulations in Synopsys HSPICE show that the proposed DNUCR latch recovers from all DNUs and can withstand large amount of injected charge. The simulation outcomes further show that the proposed DNUCR latch outperforms existing DNU‐resilient latches in terms of delay, power consumption, and power–delay–area product (PDAP), with an average of 48% reduction in delay, 22% savings in power, and 60% reduction in PDAP. The proposed DNUCR latch is also found to be the best among the existing radiation‐hardened latches in terms of charge‐to‐PDAP ratio.

Low-Complexity Double-Node-Upset Resilient Latch Design Using Novel Stacked Cross-Coupled Elements

With aggressive scaling down in integrated circuit technology, the design of double-node-upset (DNU)-resilient latches have become a major issue regarding radiation hardening by design (RHBD). The conventional DNU-resilient latches are mostly based on the Muller C-element (MCE) and the dual-interlocked storage cell (DICE) element, which exhibit severe limitations: charge sharing during the read operation at a system level and large power consumption. Overcoming these limitations, this brief proposes a DNU-resilient latch based on a novel latch element. The proposed latch fully exploits upset polarity awareness, achieving the maximum number of single-event upset (SEU)-insensitive nodes. We develop a novel double modular redundancy architecture for the DNU-resilient latch design with one SEU-immune module. Based on simulation results, the proposed latch achieves up to 27.6X average power-delay-area-product (PDAP) improvement over state-of-the-art DNU-resilient latches.

An efficient common source sense amplifier for single ended SRAM

Sense amplifiers (SA) play a vital role in supporting the read performance of static random-access memory (SRAM). Single ended SRAM has attracted importance due to low leakage current and absence of time margin compared to differential SA. This paper proposes a common source sense amplifier (CSSA) for low power single ended SRAM for read operation. The sense amplifier performs dual task by charging the bit line during pre-charge phase and amplifying the bit line during evaluation phase. The proposed CSSA shows good improvement in sensing time and power at higher number of cells per bit line (CpBL). The proposed CSSA exhibits 53%, 48%, 24%, 23%, and 41% lower sensing time for 256 CpBL and 52%, 51%, 50%, 37%, and 47% lesser power consumption than the conventional domino sensing scheme (DSS), AC coupled sense amplifier (ACSA), non-strobed regenerative sense amplifier (NSRSA), switching PMOS sense amplifier (SPSA) and trip point bit line pre-charge sensing scheme (TBPSS). The proposed CSSA occupies 18%, 25%, 53%, 61%, and 37% lesser area compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA has 88%, 88%, 85%, 91%, and 87% lesser APDP (area power delay product) compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA sensing scheme is implemented and simulated in Cadence Virtuoso tool with 45 nm technology. The simulation results of CSSA prove that the proposed CSSA sense amplifier is suitable for high speed and low power SRAM architecture.

High-efficient and error-resilient gate diffusion input-based approximate full adders for complex multistage rapid structures

Two new approximate full adders (FAs) are proposed by the multiplexers (MUXs) and OR gates with the gate diffusion input (GDI) technique. The cells are named GDI-based MUX approximate FAs (GMAFAs), GMAFA1, and GMAFA2. The threshold voltage drop of the GDI-based circuits is solved by carbon nanotube field-effect transistors (CNTFETs) technology and the dynamic threshold (DT) technique. The FAs have accurate Cout, approximate Sum, and a low number of transistors. They are low-power, high-speed, and energy-efficient for ripple-carry adders (RCAs). The GMAFA1 and GMAFA2 have a total area of 0.068 µm2 and 0.119 µm2, respectively, which demonstrate 27.8% and 54.55% improvement in power-delay-area-product (PDAP) in comparison with the best references. The results of error distance (ED), normalized mean error distance (NMED), power signal-to-noise ratio (PSNR), and energy-saving confirm the accuracy of the presented cells for image processing applications.

Area Efficient Approximate 4–2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier

Many multipliers based on approximate compressors have been developed for error-tolerant applications such as image processing to reduce power, but the combination of them has not been fully studied. This paper proposes a novel 4 gate 4-2 approximate compressor which is complementary with other compressors from earlier work and constructs a hybrid multiplier based on the compressors, a constant approximation, and error correction AND gate. According to the simulation results, the proposed hybrid approximate multiplier has excellent accuracy and electrical performance tradeoff and reduces the power-delay-area product (PDAP) by 66% with an MRED of 2.5% when compared to the exact multiplier.

High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures

Approximate computing (AC) is an emerging technique in arithmetic circuits. In this letter, a new AC-based full adder (FA) circuit is presented with 12 transistors, 150mm]Please confirm or add details for any funding or financial support for the research of this article. -160mm]If you haven’t done so already, please make sure you have submitted a video graphical abstract (GA) for your paper, along with a caption and overlay image. The GA will be displayed on your articles abstract page on IEEE Xplore. Note that captions cannot exceed 1800 characters (including spaces). Overlay images are usually a screenshot of your video that best represents the video. This is for readers who may not have access to video-viewing software. 0.239 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}^{2}$ </tex-math></inline-formula> of area, and two errors in the outputs. In the proposed FA, the gate diffusion input (GDI) and dynamic-threshold (DT) techniques are applied using the carbon nanotube field-effect transistor (CNTFET) technology. Accuracy metrics, such as normalized mean error distance (NMED) and mean relative error distance (MRED) along with circuitry parameters of power-delay-product (PDP), energy-delay-product (EDP), and power-delay-area-product (PDAP), confirm the efficiency of the proposed FA for complex structures. The proposed FA is embedded in a ripple carry adder (RCA) by various numbers of approximate bits (NABs), and then the accuracy and circuitry parameters are extracted. Compared to the state-of-the-art designs, the high-efficient behavior of the proposed FA is proved when it is used in image processing applications.

Hybrid MTJ/CNTFET-Based Binary Synapse and Neuron for Process-in-Memory Architecture

This paper proposes a reliable integrated binary synapse and neurons for hardware implementation of binary neural networks. Thanks to the nonvolatile nature of the magnetic tunnel junction ( <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MTJ</b> ) and the unique features of the carbon nanotube field-effect transistor ( <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CNTFET</b> ), the proposed design in this paper does not require external memory to store weights and also consumes low static power. Also, due to the proposed circuit structure that did not use sequential parts, the proposed circuit is immune to soft error. Because in binary neural networks, weights are limited to two values of ‘-1’ and ‘1’, the occurrence of soft errors dramatically reduces the accuracy of the network. Simulation results indicate that the proposed design in this paper consumes at least 9% lower power, occupies 34% lower area, and offers a 49% lower power delay area product ( <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PDAP</b> ). Also, Monte-Carlo simulations have been performed to study the effect of the process variation on the network. The result of the Monte-Carlo simulations shows that the proposed neuron has no logical error in 10000 simulations. Consequently, the accuracy of the network utilizing by the proposed neuron is equal to the software-implemented network and does not decrease even in the presence of process variations.

A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design

In this article, a high-performance and low-cost single-event multiple-node-upsets resilient (HLMR) latch is proposed in 55-nm CMOS technology. By using eight normal two-input Muller-C-elements (MCEs) and eight clock-gating (CG)-based two-input MCEs, a feedback loop storage module with 16 storage nodes is constructed, which makes the latch completely triple-node-upsets (TNUs) resilient. Meanwhile, through the special layout technique which guarantees the worst quadruple-node pairs as physically apart as possible, the proposed latch is completely quadruple-node-upsets (QNUs) tolerant and almost completely QNU resilient. Simulation results have validated the robustness and low cost of the proposed latch due to the use of high-speed transmission gates (TGs), CG technology, and fewer transistors. Overhead comparisons indicate that our design saves 383.53% area-power-delay product (APDP) on average and has a lower sensitivity on process, voltage and temperature (PVT) compared with other considered up-to-date multiple-node-upsets (MNUs) tolerant latches, thus providing high reliability for safety and low-cost critical applications, especially in harsh radiative environments.

A triple-node upset self-healing latch for high speed and robust operation in radiation-prone harsh-environment

With continuous advancement in technology, latches have become highly susceptible to radiation induced soft-errors such as multi-node-upsets (MNU). To effectively resilient the MNUs, this work presents a triple-node-upset (TNU) self-healing (TNUSH) latch, which performs robust operation in harsh radiation environment. The TNUSH latch mainly employs Muller C-elements and is segmented as storage cells, feedback interceptors, and the healer, forming multi-feedback interlocked loops to retain the original data after a radiation event. The self-healing capability of the proposed latch is successfully validated by the fault-injection simulation using Synopsys HSPICE. Simulation results show that the proposed latch offers highest speed of operation and has the lowest cost in terms of the power-delay-area-product (PDAP) among the existing TNU resilient latches. The proposed latch saves up to 26.64 % power and 18.47 % area compared to TNU resilient TNURL, and 92.21 % time and 88.33 % PDAP compared to the TNUTL, which is not resilient to TNU. Robustness of the proposed latch against process, voltage, and temperature variation is further assessed by Monte-Carlo simulations.

A High Performance and Low Power Triple-Node-Upset Self-Recoverable Latch Design

The charge sharing effect is becoming increasingly severe due to the continuous reduction of semiconductor process feature size. In the nanoscale digital circuit, the probability of triple-node upset (TNU) is increasing, which seriously affects the reliability of the circuit. To improve the reliability of the digital circuit, this paper presents an optimized TNU self-recoverable latch (HLTNURL). This latch consists of three dual-node-self-recoverable dual interlocked storage cells (DNSR-DICE) and one clock-gating C-element. Whenever any three nodes invert, the latch is able to self-recover to its correct logical values. The HSPICE simulation results indicate that this latch enables full self-recovery of TNU in all cases. In comparison with existing TNU self-recoverable latches, the proposed HLTNURL latch is able to reduce the power dissipation, delay, area overhead, and area-power-delay product (APDP) by 32.41%, 79.73%, 1.32%, and 88% on average. In addition, the HLTNURL latch proposed in this paper has high reliability and low sensitivity to process, voltage, and temperature (i.e., PVT) variations.

Highly reliable bio-inspired spintronic/CNTFET multi-bit per cell nonvolatile memory

This paper proposes a bio-inspired, low-cost, and highly reliable non-volatile memory design with multi-bit storage capability in one cell to answer the existing memory challenges such as high area and high power consumption. The proposed Multi-level memory (MLM) is based on magnetic tunnel junction (MTJ) as a non-volatile memory element and carbon nanotube field-effect transistors (CNTFET). MLM design provides higher data density, lower area, and lower power consumption per bit of the stored data than single-level memories (SLM). MTJs introduce nonvolatility and near-zero leakage current to the proposed MLM design, which is very important in memory cells. Moreover, as no sequential part is used in the proposed MLM, the proposed memory is also immune to energetic particle strikes. The simulation results indicate that our proposed MLM occupies at least an 80% lower area and offers a 20% lower Power Delay Product (PDP) and an 84% lower Power Delay Area Product (PDAP) than the state-of-the-art designs. Moreover, our results validate the SEU and SEMU immunity of the proposed circuit. Furthermore, the comprehensive Monte-Carlo and corner simulations ascertain the robustness of the proposed MLM memory, even in the presence of a significant process variation.

A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications

This work presents a single event double node upset (SEDNU) self-healing (DNUSH) latch to meet the high-robustness requirement of the applications used in a harsh radiation environment. The DNUSH latch is based on dual modular redundancy and mainly employs C-elements and inverters, forming multi-feedback interlocked loops to retain the correct data even after the radiation event. The self-healing capability of the proposed latch is successfully shown by the fault injection simulation using Synopsys HSPICE. Simulation results show that the proposed latch can self-heal from all SEDNUs, consumes low power even for high-speed operations, and has the least power-delay-area product (PDAP) compared to the existing SEDNU resilient latches. The proposed latch offers on average 51.25% improvement in speed, 22.67% saving in power consumption, and 59.74% lower PDAP compared to the existing SEDNU resilient latches. In addition, the sensitivity assessment of the proposed latch against the process, voltage, and temperature (PVT) variations are found to be either low or equivalent to the reference latches.

HTNURL: Design of a High-Performance Low-Cost Triple-Node Upset Self-Recoverable Latch

A high-performance and low power consumption triple-node upset self-recoverable latch (HTNURL) is proposed. It can effectively tolerate single-node upset (SNU), double-node upset (DNU), and triple-node upset (TNU). This latch uses the C-element to construct a feedback loop, which reduces the delay and power consumption by fast path and clock gating techniques. Compared with the TNU-recoverable latches, HTNURL has a lower delay, reduced power consumption, and full self-recoverability. The delay, power consumption, area overhead, and area-power-delay product (APDP) of the HTNURL is reduced by 33.87%, 63.34%, 21.13%, and 81.71% on average.

Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process

Tunnel FET is recognized as one of the most promising candidates for ultra-low power applications due to its ultra-low off current and CMOS compatibility. However, some characteristics of TFET caused by asymmetric device structure and special conduction mechanism may make conventional topologies of logic circuits no longer applicable. Our previous work has reported that TFET stacking will result in severe current degradation, which makes traditional logic cells not applicable. In this paper, two solutions are proposed: first, from a logic cell perspective, novel hybrid TFET-MOSFET topologies of standard logic cells are proposed, which achieve more than 2 times lower hardware cost and intrinsic delay, hence up to 4 times lower area-power-delay product (APDP) than that of conventional TFET logic circuits. Compared to MOSFET logic circuits, the designs achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP. Second, from a large-scale circuit perspective, an optimized digital front-end (DFE) is proposed. Taking serial peripheral interface (SPI) as an example, SPI circuit using the optimized DFE achieves 46% lower delay and 4 times lower APDP than that of traditional TFET SPI, and 3 orders of magnitude lower static power and APDP than that of MOSFET SPI.

Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance

Double-node upsets induced by the charge sharing effects are emerging as a major reliability issue in nanometer latch design. Although the existing robust latches can provide a good tolerance for double-node upsets, the implementation of these hardened latches incurs in considerable hardware penalties in terms of delay, area, and power, because they rely on traditional hardening techniques such as space redundancy. In this paper, a novel low-complexity (with respect to hardware redundancy in terms of area, delay, and power) radiation hardened (RH) latch is proposed; this latch is based on the dual interlocked storage cell (DICE). Based on the radiation upset mechanism, in particular the upset polarity of the transient pulse, the proposed RH latch can effectively reduce the number of protected nodes (sensitive nodes), as well as the number of transistors, thus reducing circuit overhead. At the same, a single node upset in any sensitive node and a double-node upset in any sensitive node pair can be recovered, because at least two stable nodes can retain the values even when a double-node upset occurs. The results are based on mapping designs to TSMC 65 nm commercial CMOS process design kit (PDK) and demonstrate that the proposed RH latch incurs in significant reductions in terms of propagation delay, circuit area, and power-delay-area product (PDAP), compared with existing hardened latches. The tolerance functionality of the proposed latch is successfully validated by fault injection. In addition, the impact of variations and process corners is assessed using Monte Carlo (MC) simulation. The simulation results confirm that the proposed latch can also tolerate all upsets, even under extreme values of process variations.