Area Network System Research Articles

Polygonal Patch Antennas for Wireless Communications

An effective design of polygonal patch antennas with multifrequency or broad-band operation modes for wireless communications is presented in this paper. It is shown how polygonal patches with suitable features may be obtained after a proper perturbation of conventional rectangular geometries, which inherently present poor bandwidth performances. These perturbed irregular geometries may support multiple resonances and, thus, may present a broad-band or multifrequency operation mode, even employing conventional patch antennas with a single dielectric substrate. These polygonal patches are efficiently analyzed through a numerical code based on the method of moments, with entire domain basis functions that accurately describe the radiation mechanism. After the presentation of the analysis and design techniques, some antenna layouts for modern wireless communication systems will be proposed. Such antennas are designed for both universal mobile telecommunication system and wireless local area network portable equipment with real-life finite ground planes.

Robust synchronization and channel estimation for the OFDM-based WLAN systems

As an effective technique for combating multipath fading and for high data rate transmission over wireless channels, orthogonal frequency division multiplexing (OFDM) is extensively used in wireless local area network (WLAN) systems to support high performance bandwidth-efficient multimedia services. In this paper, novel synchronization and channel estimation schemes are proposed for the OFDM-based WLAN systems. Analyses and simulation results show that the proposed schemes exhibit good performances and are robust in harsh fading channel environments and low signal-to-noise ratio (SNR) conditions.

Cluster communication protocols for parallel-programming systems

Clusters of workstations are a popular platform for high-performance computing. For many parallel applications, efficient use of a fast interconnection network is essential for good performance. Several modern System Area Networks include programmable network interfaces that can be tailored to perform protocol tasks that otherwise would need to be done by the host processors. Finding the right trade-off between protocol processing at the host and the network interface is difficult in general. In this work, we systematically evaluate the performance of different implementations of a single, user-level communication interface. The implementations make different architectural assumptions about the reliability of the network and the capabilities of the network interface. The implementations differ accordingly in their division of protocol tasks between host software, network-interface firmware, and network hardware. Also, we investigate the effects of alternative data-transfer methods and multicast implementations, and we evaluate the influence of packet size. Using microbenchmarks, parallel-programming systems, and parallel applications, we assess the performance of the different implementations at multiple levels. We use two hardware platforms with different performance characteristics to validate our conclusions. We show how moving protocol tasks to a relatively slow network interface can yield both performance advantages and disadvantages, depending on specific characteristics of the application and the underlying parallel-programming system.

End-to-end performance of 10-gigabit ethernet on commodity systems

Apart form the success in local-area networks (LANs) and system-area networks and anticipated success in metropolitan and wide area networks (MANs and WANs), Ethernet continues to evolve to meet the increasing demands of packet-switched networks. Although the recently ratified 10-Gigabit Ethernet standard differs from earlier Ethernet standards, primarily in that 10GbE operates only over fiber and only in full-duplex mode, the differences are largely superficial. More importantly, l0GbE does not make obsolete current investments in network infrastructure. The 10GbE standard ensures interoperability not only with existing Ethernet but also with other networking technologies such as Sonet, thus paving the way for Ethernets expanded use in MANs and WANs. The world's first host-based 10GbE adapter, officially known as the Intel PRO/10GbE LR server adapter, introduces the benefits of l0GbE connectivity into LAN and system-area network environments, thereby accommodating the growing number of large-scale cluster systems and bandwidth-intensive applications, such as imaging and data mirroring. The 10GbE controller is optimized for servers that use the I/O bus backplanes of the peripheral component interface (PCI) and its higher speed extension, PCI-X.

A clustering approach for identifying and quantifying irregularities in interconnection networks

Support for arbitrary topologies has become more popular for system-area networks but very little has been done in trying to characterize their behavior and performance. Traditional parameters like diameter and bisection width are not sufficient for characterizing the irregularities that abound in such networks and fail to give much insight into throughput performance. A clustering approach for partitioning a network into clusters of richly-connected regions is proposed as a means of defining two performance-correlated characterization metrics: intercluster bandwidth index and intercluster link-cost index. The two characterization metrics are shown to have a strong correlation to saturation throughput when link and load distribution of a network is imbalanced. Simulation results also show that the clustering algorithm can be applied to a variety of network configurations and traffic scenarios, particularly irregular ones. With the proposed characterization metrics that correlate more strongly with performance, it is possible to classify networks into categories having similar performance.

Packetization and routing analysis of on-chip multiprocessor networks

Some current and most future systems-on-chips use and will use network architectures/protocols to implement on-chip communication. On-chip networks borrow features and design methods from those used in parallel computing clusters and computer system area networks. They differ from traditional networks because of larger on-chip wiring resources and flexibility, as well as constraints on area and energy consumption (in addition to performance requirements). In this paper, we analyze different routing schemes for packetized on-chip communication on a mesh network architecture, with particular emphasis on specific benefits and limitations of silicon VLSI implementations. A contention-look-ahead on-chip routing scheme is proposed. It reduces the network delay with significantly smaller buffer requirement. We further show that in the on-chip multiprocessor systems, both the instruction execution inside node processors, as well as data transaction between different processing elements, are greatly affected by the packetized dataflows that are transported on the on-chip networks. Different packetization schemes affect the performance and power consumption of multiprocessor systems. Our analysis is also quantified by the network/multiprocessor co-simulation benchmark results.

Peak-to-average power control for multiple-antenna HIPERLAN/2 and IEEE802.11a systems

A combination of multi-input multi-output (MIMO) signal processing with orthogonal frequency division multiplexing (OFDM) is regarded as a promising solution for enhancing the performance of next generation wireless local area network (WLAN) systems. This paper evaluates the peak-to-average power ratio (PAR) performance in a MIMO OFDM-based WLAN system using a space-time block code (STBC). The investigated PAR control schemes, which are originally based on the selective mapping (SLM) and partial transmit sequence (PTS) approaches, select the transmitted sequence with the lowest average PAR over all transmit antennas and retrieve the side information (SI) very accurately at the expense of a slight degradation of the PAR performance. The low probability of false SI can improve the overall detection performance of the MIMO-WLAN system encountered with erroneous SI compared to the ordinary SLM and PTS approaches, respectively.

Anchored opportunity queueing: a low-latency scheduler for fair arbitration among virtual channels

Many wormhole interconnection networks for parallel systems, and more recently system area networks, implement virtual channels to provide a number of services including improved link utilization and lower latencies. The forwarding of flits from the virtual channels on to the physical channel is typically accomplished using flit-based round-robin (FBRR) scheduling. This paper presents a novel scheduling strategy, anchored opportunity queueing ( AOQ), which preserves the throughput and fairness characteristics of FBRR while significantly reducing the average delay experienced by packets. The AOQ scheduler achieves lower average latencies by trying, as far as possible, to complete the transmission of a complete packet before beginning the transmission of flits from another packet. The AOQ scheduler achieves provable fairness in the number of opportunities it offers to each of the virtual channels for transmissions of flits over the physical channel. We prove this by showing that the relative fairness bound, a popular measure of fairness, is a small finite constant in the case of the AOQ scheduler. Finally, we present simulation results comparing the delay characteristics of AOQ with other schedulers for virtual channels. The AOQ scheduler is simple to implement in hardware, and also offers a practical solution in other contexts such as in scheduling ATM cells in Internet backbone switches.

Measurements of parameter imbalances in OFDM-based WLAN

We measure the effect of an imperfect channel estimation and carrier frequency offset on the performance of an OFDM-based wireless local area network (WLAN) system. For the performance evaluation, the average bit error rate (BER) expression is derived in the presence of imperfect channel information, including both inherent estimation error and imperfect windowing error, derived in a mismatched channel separation. From numerical results, the inherent channel estimation error is found to be a dominating term in the system performance, compared to the other imperfections. The provided results work for the performance evaluation of the OFDM-based WLAN physical layer (PHY).

Design and implementation of a user‐level Sockets layer over Virtual Interface Architecture

AbstractThe Virtual Interface Architecture (VIA) is an industry standard user‐level communication architecture for system area networks. The VIA provides a protected, directly‐accessible interface to a network hardware, removing the operating system from the critical communication path. In this paper, we design and implement a user‐level Sockets layer over VIA, named SOVIA (Sockets Over VIA). Our objective is to use the SOVIA layer to accelerate the existing Sockets‐based applications with a reasonable effort and to provide a portable and high‐performance communication library based on VIA to application developers.SOVIA realizes comparable performance to native VIA, showing a minimum one‐way latency of 10.5 $\mu$s and a peak bandwidth of 814 Mbps on Giganet's cLAN. We have shown the functional compatibility with the existing Sockets API by porting File Transfer Protocol (FTP) and Remote Procedure Call (RPC) applications over the SOVIA layer. Compared to the Giganet's LAN Emulation (LANE) driver which emulates TCP/IP inside the kernel, SOVIA easily doubles the file transfer bandwidth in FTP and reduces the latency of calling an empty remote procedure by 77% in RPC applications. Copyright © 2003 John Wiley & Sons, Ltd.

Real-time wormhole channels

For real-time communication, we must be able to guarantee timely delivery of messages. In recent years, improvements in technology have made possible switch-based local area networks (LANs) and system area networks (SANs) that use wormhole switching, a pipelined switching technique which permits significantly shorter network latencies and higher throughputs than traditional store-and-forward packet switching. This paper proposes a model for real-time communication in such wormhole networks based on the use of real-time wormhole channels, which are simplex virtual circuits in wormhole networks with certain real-time guarantees. A distinguishing feature of our model is that it can be used in existing wormhole networks without any special hardware support. Preliminary delay analysis and properties are shown for the proposed real-time wormhole channel model. A practical quadratic time complexity algorithm is shown for determining the feasibility of a set of wormhole channels. Finally, as an example of the utility of our model, actual parameter values obtained from experiments on a Myrinet switch-based network are used to determine if real-time guarantees are possible for an example set of real-time traffic streams intermixed with nonreal-time traffic.

Using System Emulation to Model Next-Generation Shared Virtual Memory Clusters

Recently much effort has been spent on providing a shared address space abstraction on clusters of small-scale symmetric multiprocessors. However, advances in technology will soon make it possible to construct these clusters with larger-scale cc-NUMA nodes, connected with non-coherent networks that offer latencies and bandwidth comparable to interconnection networks used in hardware cache-coherent systems. The shared memory abstraction can be provided on these systems in software across nodes and hardware within nodes. Recent simulation results have demonstrated that certain features of modern system area networks can be used to greatly reduce shared virtual memory (SVM) overheads [5,19]. In this work we leverage these results and we use detailed system emulation to investigate building future software shared memory clusters. We use an existing, large-scale hardware cache-coherent system with 64 processors to emulate a complete future cluster. We port our existing infrastructure (communication layer and shared memory protocol) on this system and study the behavior of a set of real applications. We present results for both 32- and 64-processor system configurations. We find that: (i) System emulation is invaluable in quantifying potential benefits from changes in the technology of commodity components. More importantly, it reveals potential problems in future systems that are easily overlooked in simulation studies. Thus, system emulation should be used along with other modeling techniques (e.g., simulation, implementation) to investigate future trends. (ii) Our work shows that current SVM protocols can only partially take advantage of faster interconnects and wider nodes due to operating system and architectural implications. We quantify the related issues and identify the areas where more research is required for future SVM clusters.

A seamless mobile VPN data solution for CDMA2000,* UMTS, and WLAN users

Mobile virtual private networks (MVPNs) can provide remote users with easy, secure high-speed access to their enterprise network resources. There is a tremendous market opportunity for operators who can meet the needs of these users. Third-generation (3G) systems, such as code division multiple access (CDMA) (3G-1X and 1xEV-DO) or universal mobile telecommunications system (UMTS), and IEEE 802.11b wireless local area network (WLAN) systems have complementary strengths. For end users, integrating these systems provides ubiquitous high-speed data coverage, continuous selection of the highest possible data rates, and seamlessly maintained user VPN sessions when moving between air interface technologies. For operators, they enable integrated billing and offload 3G network capacity for higher revenue voice subscribers. This paper shows how Lucent Technologies uses IETF mobile IP (MIP), IP security (IPSec), and multiple tunneling protocol standards to offer a comprehensive transport layer solution across 3G and WLAN air interface technologies. Shared requirements for accounting, authentication, security, and confidentiality in 3G and WLAN core data networks are also addressed.

Data monitoring in high-performance clusters for computing applications

The shared memory in a LAN-like environment (SMiLE) project at Lehrstuhl fur Rechnertechnik und Rechnerorganisation, Technical University of Munich (LRR-TUM) investigates in high-performance cluster computing using system area networks. In the context of this project, a hardware monitor is being developed to observe the system area network (SAN) traffic. This hardware monitor is, therefore, capable of delivering detailed information about the run-time communication behavior of applications running on SMiLE clusters. The central part of this monitor consists of a content-addressable counter array managing a small working set of the most recently referenced memory regions.

A new injection limitation mechanism for wormhole networks

Wormhole switching has been widely applied to the interconnection networks of parallel systems as well as System Area Networks, and Local Area Networks, largely because of its efficiency and performance merits. Examples include the Myrinet of Myricom Inc as well as most of the newly developed parallel systems. True Fully Adaptive Routing (TFAR) Algorithms have demonstrated their suitability for wormhole switched networks due to their unrestricted Adaptivity and moderate resource requirements. Wormhole switching has proven to be the most popular switching technique targeted for interconnection networks of message-passing multicomputers as well as SANs, and LANs. TFAR Algorithms have also been gaining favor for application in wormhole switched networks due to their highly adaptive and moderate hardware requirements. Wormhole switched networks have associated drawbacks however, as they generally suffer from performance degradation beyond the saturation point due to channel congestion. Fully adaptive algorithms are vulnerable to cyclic dependencies, which are precursors to deadlock formations. Consequently the frequent occurrence of deadlocks can further degrade the performance and stability characteristics of these networks. Injection limitation techniques were recently introduced in an attempt to countermeasure these drawbacks and effectively contain their impact on the performance of the network. This paper proposes a new injection limitation mechanism and its performance evaluation. The new mechanism is named Congestion Level Injection Control (CLIC). This mechanism attempts to provide a solution for these problems and improve the overall performance of the network. The new mechanism is centered on congestion level estimation in the network using only local information at each node. The mechanism subsequently prevents the injection of new packets if the network is deemed to be highly congested or possibly close to its saturation point. The performance of the CLIC mechanism has been compared with other competing schemes. Our results have shown that CLIC has superior performance when compared to other competing schemes.

Flow Control in ServerNet ® Clusters

This paper investigates the performance implications of several end-to-end flow control protocols in clusters based on the ServerNet® system-area network. The Static Window (SW) and Packet Pair (PP) flow control protocols are studied. Based on them, the Simplified Packet Pair (SPP) and the Alternating Static Window (ASW) protocols are defined. Previously, it has been proven that PP is stable for store-and-forward networks based on Rate Allocation Servers. The applicability of PP to wormhole-routing networks is studied. Simulation results for the performance characteristics are obtained and evaluated. It is shown that if high throughput is desired, ASW is the best method for controlling the average latency. On the other hand, if low throughput is acceptable, SPP can be applied to maintain low latencies.

Streaming Video with Storage Area Networks

The emergence of digital media integrated with storage area network (SAN) systems creates one of the most significant technological changes experienced by the broadcast, entertainment, and media industries. A new set of variables and business issues are emerging that impact the entire video distribution chain for production houses, content aggregators, broadcasters, and service providers. As a result, industry players must adapt their IT infrastructures for new challenges such as the transition from analog-to-digital formats (including HDTV), new codecs, implementing media asset management systems, digital rights management, IP and ATM video transmission, and transitioning from tape to SAN-based disk architectures. This paper will examine the video supply chain management workflow process in the media and broadcast environments and the impact of integrating storage area networks for streaming video.

Design and implementation of efficient communication abstractions on the Virtual Interface Architecture: Stream sockets and RPC experience

AbstractThe emergence and standardization of system area networks (SANs) has provided distributed applications with a medium for high‐bandwidth, low‐latency communication. Standard user‐level networking architecture such as the Virtual Interface (VI) Architecture enables distributed applications to perform low overhead communication over SANs. The VI Architecture significantly reduces system processing overheads and provides each consumer process with a protected, directly accessible interface to the network hardware. Developing distributed applications using low‐level primitives provided by user‐level networking architecture like the VI Architecture is complex and requires significant effort.This paper describes how high‐level communication paradigms like stream sockets and remote procedure call (RPC) can be efficiently built over the VI Architecture. To evaluate performance benefits for standard client–server and multi‐threaded environments, our focus is on off‐the‐shelf sockets and RPC interfaces and commercially available VI Architecture‐based SANs. The key design techniques developed in this paper include credit‐based flow control, decentralized user‐level protocol processing, caching of pinned communication buffers, and deferred processing of completed send operations.In the experimental evaluation, the one‐way bandwidth achieved by stream sockets over VI Architecture was three to four times better than the bandwidth achieved by running legacy protocols over the same interconnect. On the same SAN, high‐performance stream sockets and RPC over VI Architecture achieve significantly better (between 2× and 3× less) latency than conventional stream sockets and RPC over standard networking protocols in a Windows NT™ 4.0 environment. Furthermore, our high‐performance RPC transparently improved the network performance of the distributed component object model (DCOM) by a factor of two to three. Copyright © 2001 John Wiley & Sons, Ltd.

Accelerating shared virtual memory via general-purpose network interface support

Clusters of symmetric multiprocessors (SMPs) are important platforms for high-performance computing. With the success of hardware cache-coherent distributed shared memory (DSM), a lot of effort has also been made to support the coherent shared-address-space programming model in software on clusters. Much research has been done in fast communication on clusters and in protocols for supporting software shared memory across them. However, the performance of software virtual memory (SVM) is still far from that achieved on hardware DSM systems. The goal of this paper is to improve the performance of SVM on system area network clusters by considering communication and protocol layer interactions. We first examine what are the important communication system bottlenecks that stand in the way of improving parallel performance of SVM clusters; in particular, which parameters of the communication architecture are most important to improve further relative to processor speed, which ones are already adequate on modern systems for most applications, and how will this change with technology in the future. We find that the most important communication subsystem cost to improve is the overhead of generating and delivery interrupts for asynchronous protocol processing. Then we proceed to show, that by providing simple and general support for asynchronous message handling in a commodity network interface (NI) and by altering SVM protocols appropriately, protocol activity can be decoupled from asynchronous message handling, and the need for interrupts or polling can be eliminated. The NI mechanisms needed are generic, not SVM-dependent. We prototype the mechanisms and such asynchronous home-basedLRCprotocol, calledGeNIMA(GEneral-purpose Network Interface support for shared Memory Abstractions), on a cluster of SMPs with a programmable NI. We find that the performance improvements are substantial, bringing performance on a small-scale SMP cluster much closer to that of hardware-coherent shared memory for many applications, and we show the value of each of the mechanisms in different applications.

High-Fidelity Modelling and Simulation of Myrinet System Area Networks

This paper presents a high-fidelity, event-driven model for performance analysis of various applications on Myrinet system area networks (SANs). The model, designed for the Block-Oriented Network Simulator (BONeS) commercial CAD environment for discrete-event simulation, is accurate down to the Myrinet character level, and supports a wide variety of topologies and parameter permutations. An analytical model is also presented by which the simulation model is verified, and validation of the simulation model is achieved through comparisons with experimental testbed results on both networking and parallel computing tests. In addition, a case study on performance analysis of Myrinet-based networks and clustered computers is included. This case study examines the impact of Myrinet data rate and buffer size on communication and computing performance, further demonstrating the flexibility and versatility of the new simulation model.