Adder Architectures Research Articles

A simple and high speed CMOS carry chain adder architecture

A simple and high speed adder architecture is presented in this paper. This adder uses pass transistor pairs to make a fast CMOS carry chain as used by the Manchester carry chain technique. It uses less hardware, and is faster than conventional ripple-carry adders. It is also significantly faster than the sign-select adder recently described by Srinivas et al. for word lengths less than or equal to 8, and is slightly faster than this adder for word lengths greater than 8. The structure, however, is simpler and more regular. This adder is well suited for VLSI implementation, and provides a useful trade-off between speed and complexity.

Arithmetic operations using binary encoding modified-signed-digit system

The modified-signed-digit (MSD) number system offers parallel carry-free addition and subtraction, which is attractive to the design of a fully parallel processor. A two-state MSD adder/subtractor using binary encoding modified-signed-digit system is proposed, in which twelve substitution rules are employed in the MSD adder/subtractor. Using the binary encoding MSD scheme, each stage of the MSD arithmetic operations is realized by simple logic operations, therefore, its optical implementation can use well-developed binary optical components. An optical architecture of the two-stage MSD adder using programmable triple-in logic gate is presented and preliminary results are presented.

A fast VLSI adder architecture

An architecture for performing fixed-point, high-speed, two's-complement, bit-parallel addition by using the carry-free property of redundant arithmetic and a fast parallel redundant-to-binary conversion scheme is presented. The internal numbers are represented in radix-2 redundant digit form, and the inputs and the output of the adder are represented in two's-complement binary form. The adder operands are added first in a radix-2 redundant adder to produce the result in radix-2 digit (-1, 0, 1) form. This result is converted to two's-complement binary form using the parallel conversion scheme. The high-speed conversion for long words is achieved through the use of a novel sign-select operation. The proposed adder, referred to as the sign-select conversion adder, is faster than all previous high-speed two's-complement binary adders for large word lengths. The implementation is highly regular with repeated modules and is very well suited for VLSI implementation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Butterfly interconnection implementation for an n-bit parallel ripple carry full adder

Free-space optical interconnections are important both in massive digital optical computing and in communication systems. The optical butterfly interconnection has many advantages over other interconnections in implementing various basic logic functions such as addition, subtraction, multiplication. This paper starts with the conventional Karnaugh maps and Boolean algebra to implement a parallel n-bit ripple carry full adder by the use of multilayer butterfly interconnection networks. Then we describe in detail the design and architecture of the full adder and provide accurate interconnection networks and the structures or patterns of key devices such as the masks to implement AND and OR operations in this calculation. Finally, we discuss development of the interconnection in implementing logic operations.

A 6.5-ns GaAs 20*20-b parallel multiplier with 67-ps gate delay

The performance and yield of LSI circuits have been characterized over a wide variation in processing parameters and power supply voltage, and over the military temperature range using 4*4-, 8*8-, 12*12-, 16*16-, and 20*20-b multipliers. These parallel array multipliers with carry-save adder architecture have been implemented in low-power GaAs enhancement/depletion (E/D) direct-coupled FET logic (DCFL). The circuits were fabricated with a multifunction self-aligned gate process, which features a buried p-layer for high yield and manufacturability. Worst-case multiplication times ranging from 870 ps (51 ps/gate) for the 4*4-b, to 6.48 ns (67 ps/ gate) for the 20*20-b multiplier were obtained, with the fastest extracted gate delays yet reported for LSI circuits. The 20*20-b multiplier, with 18573 active devices (4902 logic gates), shows a wafer-probe yield as high as 61% on the best-yielding wafers. It is concluded that the E/D DCFL family is capable of providing LSI circuits operating over a wide variation in power-supply voltage and over the full military temperature range. >

Fast Fourier transforms with factored residue look-up tables

The implementation of fast Fourier transforms (FFTs) via the use of residue factored look-up tables (FLUTs) is investigated. The principles of FLUTs are reviewed, and a gate-level pipelined adder architecture is presented. The basics of the quadratic residue system (QRNS) are then discussed, and FLUT-based gatelevel pipelined architectures are presented for binary-to-QRNS and QRNS-to-binary converters as well as for FFT butterflies. The Despain small integer approximations are used to represent the FFT complex rotations, each of which is expressed via a linear combination of common angles. The QRNS FLUT FFT performance is measured via a normalized mean square error (MSE) figure, which is estimated via computer simulations performed for 16- and 32-point QRNS FFTs in conjunction with various input signals and different approximation accuracy. Based on these results the largest FLUT FFT order, for which an MSE of <10(-8) can be supported, is estimated. The overall system gate complexity is then calculated and compared with that required by the equivalent conventional digital implementation.

High-speed CMOS adder and multiplier modules for digital signal processing in a semicustom environment

For the realization of digital filters in a semicustom environment, high-performance adder and multiplier modules have been developed. These modules define the performance limits for digital finite impulse response (FIR) filters. The Gate Forest semicustom environment is a sea-of-gates-type transistor array. It supports the implementation of dynamic (domino) CMOS logic circuits. The circuit-design technique is applicable to compact high-speed designs. The realized dynamic adder architecture consists of a 2-b group adder and a Manchester carry chain (MCC). For an N-b addition this results in a N/2-b carry lookahead path. This dynamic adder scheme can be expanded into 4-b group adder modules. The multiplier module is a combination of a modified Booth-coded static adder array with a final dynamic MCC adder. The multiplier is clocked with a single (symmetric) clock signal. The clock signal is divided into a precharge pulse, in which the static part of the multiplier added array is evaluated, and an evaluation phase for the generation of the multiplication result (least significant bits). A 16-b*16-b multiplier based on this architecture runs with a 40-MHz system clock. The first chips have been processed in a 2- mu m CMOS double-metal technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>