A 6.5-ns GaAs 20*20-b parallel multiplier with 67-ps gate delay

Abstract

The performance and yield of LSI circuits have been characterized over a wide variation in processing parameters and power supply voltage, and over the military temperature range using 4*4-, 8*8-, 12*12-, 16*16-, and 20*20-b multipliers. These parallel array multipliers with carry-save adder architecture have been implemented in low-power GaAs enhancement/depletion (E/D) direct-coupled FET logic (DCFL). The circuits were fabricated with a multifunction self-aligned gate process, which features a buried p-layer for high yield and manufacturability. Worst-case multiplication times ranging from 870 ps (51 ps/gate) for the 4*4-b, to 6.48 ns (67 ps/ gate) for the 20*20-b multiplier were obtained, with the fastest extracted gate delays yet reported for LSI circuits. The 20*20-b multiplier, with 18573 active devices (4902 logic gates), shows a wafer-probe yield as high as 61% on the best-yielding wafers. It is concluded that the E/D DCFL family is capable of providing LSI circuits operating over a wide variation in power-supply voltage and over the full military temperature range. >