S-box Architecture Research Articles

Novel Substitution Box Architectural Synthesis for Lightweight Block Ciphers

This paper proposes three novel Substitution box (S-box) architectures for lightweight block ciphers. The proposed S-box architectures are based on Boolean decomposition to achieve the design tradeoffs. Absorption of the Terminal Nodes property, positive Davio expansion, and Shannon decomposition are explored for the three S-box architectures. The proposed S-box variants are included in the SPN layer of the Midori-64 block cipher to validate their utility for a lightweight cipher. Also, to demonstrate the generality of the proposed logic decomposition approaches, the proposed work is expanded to the composite field architectures for the S-box of AES-128. Compared with state-of-the-art designs, the proposed designs exhibit a reduction of 66%, 36%, and 21% for energy, delay, and power metrics.

Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers

Fault attacks pose a potent threat to modern cryptographic implementations, particularly those used in physically approachable embedded devices in IoT environments. Information security in such resource-constrained devices is ensured using lightweight ciphers, where combinational circuit implementations of SBox are preferable over look-up tables (LUT) as they are more efficient regarding area, power, and memory requirements. Most existing fault analysis techniques focus on fault injection in memory cells and registers. Recently, a novel fault model and analysis technique, namely Semi-Permanent Stuck-At (SPSA) fault analysis, has been proposed to evaluate the security of ciphers with combinational circuit implementation of Substitution layer elements, SBox. In this work, we propose optimized techniques to recover the key in a minimum number of ciphertexts in such implementations of lightweight ciphers. Based on the proposed techniques, a key recovery attack on the NIST lightweight cryptography (NIST-LWC) standardization process finalist, Elephant AEAD, has been proposed. The proposed key recovery attack is validated on two versions of Elephant cipher. The proposed fault analysis approach recovered the secret key within 85 − 240 ciphertexts, calculated over 1000 attack instances. To the best of our knowledge, this is the first work on fault analysis attacks on the Elephant scheme. Furthermore, an optimized combinational circuit implementation of Spongent SBox (SBox used in Elephant cipher) is proposed, having a smaller gate count than the optimized implementation reported in the literature. The proposed fault analysis techniques are validated on primary and optimized versions of Spongent SBox through Verilog simulations. Further, we pinpoint SPSA hotspots in the lightweight GIFT cipher SBox architecture. We observe that GIFT SBox exhibits resilience towards the proposed SPSA fault analysis technique under the single fault adversarial model. However, eight SPSA fault patterns reduce the nonlinearity of the SBox to zero, rendering it vulnerable to linear cryptanalysis. Conclusively, SPSA faults may adversely affect the cryptographic properties of an SBox, thereby leading to trivial key recovery. The GIFT cipher is used as an example to focus on two aspects: i) its SBox construction is resilient to the proposed SPSA analysis and therefore characterizing such constructions for SPSA resilience and, ii) an SBox even though resilient to the proposed SPSA analysis, may exhibit vulnerabilities towards other classical analysis techniques when subjected to SPSA faults. Our work reports new vulnerabilities in fault analysis in the combinational circuit implementations of cryptographic protocols.

Efficient hardware mapping of Boolean substitution boxes based on functional decomposition for RFID and ISM band IoT applications

This paper investigates three substitution box (S-box) designs for lightweight ciphers. The proposed designs involve functional decomposition, which is preferable as compared to the look-up tables or logic gates-based S-box designs due to their advantages, as outlined in this paper. The aim is to reduce the number of literals at the input of the S-box to achieve resource reduction in the overall circuit design of the encryption algorithms. The proposed S-box architectures provide optimized resource mapping for specific target hardware, and high throughput along with lesser energy consumption compared to state-of-the-art designs. The proposed S-box designs are applied to the substitution layers of symmetric lightweight block ciphers with a standard security level. In order to be fair in comparison, the overall cipher designs are targeted for similar FPGA-based implementation as used in existing works, while the architectures of the individual 4-bit S-boxes are evaluated using SAED90 nm standard cell libraries. The performance of the proposed S-box designs is observed to be superior at RFID and ISM frequency ranges which can be deployed in applications constrained to low resources as well as demanding high performance and medium security.

FPGA modeling of a novel fully-synthesizable and secure TRNG based on key-dependent s-box

In this study, the Field Programmable Gate Array (FPGA) implementation of a True Random Number Generator (TRNG) using dynamic key-based s-box architecture as a post-processing technique is presented. In the proposed architecture, the post-processing method of TRNG consists of two different functions, in a total of 32x32 (32-bit input & 32-bit output), containing four independent 8x8 (8-bit input & 8-bit output) s-boxes. Raw random numbers are subjected to three-stage substitution operations in these functions, and their statistical properties are cryptographically improved. The post-processing unit of TRNG is compressionless as the s-boxes are 8 x 8. Thanks to this distinctive feature of the proposed method, TRNG can reach a final output bit rate of 250 Mbps with an entropy of 0.99. With the same output bit rate, TRNG passes the National Institute of Standard and Technology (NIST) Special Publication (SP) 800-22 statistical randomness evaluation tests with success above the minimum confidence interval of 0.9805. In addition to the NIST tests, bias, entropy, correlation, chi-square, and true randomness analyses are also given for TRNG's cryptographic verification. Besides to the statistical requirements, cost and performance analyses for TRNG are also presented in the study. The estimated dynamic power consumption for TRNG needing a low chip area of 2% (3221 LEs) for hardware implementation, is measured as 10.2 mW. The final results show that TRNG has high security and efficiency standards and can be used successfully in embedded cryptographic applications.

Novel Low-Power Construction of Chaotic S-Box in Multilayer Perceptron.

Multilayer perceptron is composed of massive distributed neural processors interconnected. The nonlinear dynamic components in these processors expand the input data into a linear combination of synapses. However, the nonlinear mapping ability of original multilayer perceptron is limited when processing high complexity information. The introduction of more powerful nonlinear components (e.g., S-box) to multilayer perceptron can not only reinforce its information processing ability, but also enhance the overall security. Therefore, we combine the methods of cryptography and information theory to design a low-power chaotic S-box (LPC S-box) with entropy coding in the hidden layer to make the multilayer perceptron process information more efficiently and safely. In the performance test, our S-box architecture has good properties, which can effectively resist main known attacks (e.g., Berlekamp Massey-attack and Ronjom-Helleseth attack). This interdisciplinary work can attract more attention from academia and industry to the security of multilayer perceptron.

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$((2^{2})^{2})$ </tex-math></inline-formula> , is reduced. The squaring and multiplication with constant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> in GF <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$((2^{2})^{2})$ </tex-math></inline-formula> are combined and optimized as well. Moreover, the multiplicative inversion in GF <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$((2^{2})^{2})$ </tex-math></inline-formula> is manually optimized. Furthermore, the S-box and inverse S-box are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.

Compact Reconfigurable Architecture for Sosemanuk Stream Cipher

Sosemanuk is word oriented synchronous stream cipher capable to produce 32 bit ciphertext. It uses variable key from 128 bit to 256 bit and publically known Initialization Vector (IV) of 128 bit. Sosemanuk is one of the finalists in Profile 1 of the eSTREAM Portfolio. This cipher targets to avoid structural properties of SNOW2.0 to improve its efficiency by reducing the internal state size. It also uses reduced round Serpent24 block cipher to provide secure and efficient key loading process. This paper presents compact architecture for Sosemanuk stream cipher. The proposed architecture uses compact S-box architecture and compact modulo adders designed using CLA. The proposed compact S-box minimizes resources utilized without affecting performance. Proposed modulo adder architecture minimizes resources used as compared to conventional CLA implementation. The algorithm was designed by using VHDL language with CAD tool Xilinx ISE design suite 13.2 and implemented on Xilinx Virtex XC5VFX100E FPGA device. The proposed architecture achieved throughput of 4.281 Gbps at clock frequency of 133.788 MHz

Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems

The hardware footprint for S-box specification in lightweight block cipher as appropriate to IoT and CPS information security systems is presented in this paper. The S-box Boolean function in the lightweight block cipher is defined using the Reed-Muller structure. A Rule Based–Common Sub-structure Sharing Optimization (RB-CSSO) algorithm has been proposed towards improving the performance efficiency of Reed-Muller structure. This novel hybrid RB-CSSO optimization mechanism first transforms the direct Positive Polarity Reed Muller (PPRM) S-box representation into Mixed Polarity Reed-Muller (MPRM) S-box architecture using local rule based transformation. Secondly, the Common Sub Term (CST) and Common Sub-expression (CSE) merging/elimination are employed over the resulting MPRM structure. The combined rule-based transformation and the common sub-function sharing demonstrate an overall reduction in area, delay and power of the Reed-Muller S-box structure. Both the theoretical analysis and the experimental verification demonstrate reduction in area and delay of S-box. Post synthesis results based on ASIC standard cell based implementations have been used to analyze area, delay and power values across Process, Voltage and Temperature (PVT) corners for a wide range of operating conditions. Extensive comparisons between direct PPRM and optimized MPRM implementations have been carried out. The post layout simulations of S-box structures realized show the advantages of lower area-delay product, power-area product and power-delay product. This work thus authenticates the application of proposed structure for lightweight, resource constrained security systems. Industry standard full suite of Cadence® tools have been employed in the simulations using 65 nm TCBN65GPLUS standard cells of TSMC technology library.

An Optimized Design for Compact Masked AES S-Box Based on Composite Field and Common Subexpression Elimination Algorithm

As the only nonlinear operation, masked S-box is the core to resist differential power attack (DPA) for advanced encryption standard (AES) cipher chips. In order to suit for the resource-constrained applications, a compact masked S-box based on composite field is proposed in this paper. Firstly, the architecture of masked S-box is designed with composite field masking method. Secondly, four masked S-boxes based on GF ((2[Formula: see text], which are based on four basis methods with the optimal coefficient and the corresponding optimal root, are implemented and optimized by the delay-aware common subexpression elimination (DACSE) algorithm. Finally, experimental results show that, while maintaining the DPA-resistance performance, our best masked S-box achieves better area performance with the fastest speed compared with the existing works. Therefore, our masked S-box is suitable for resource-constrained applications with fast speed requirements.

Lightweight S-Box Architecture for Secure Internet of Things

Lightweight cryptographic solutions are required to guarantee the security of Internet of Things (IoT) pervasiveness. Cryptographic primitives mandate a non-linear operation. The design of a lightweight, secure, non-linear 4 × 4 substitution box (S-box) suited to Internet of Things (IoT) applications is proposed in this work. The structure of the 4 × 4 S-box is devised in the finite fields GF (24) and GF ((22)2). The finite field S-box is realized by multiplicative inversion followed by an affine transformation. The multiplicative inverse architecture employs Euclidean algorithm for inversion in the composite field GF ((22)2). The affine transformation is carried out in the field GF (24). The isomorphic mapping between the fields GF (24) and GF ((22)2) is based on the primitive element in the higher order field GF (24). The recommended finite field S-box architecture is combinational and enables sub-pipelining. The linear and differential cryptanalysis validates that the proposed S-box is within the maximal security bound. It is observed that there is 86.5% lesser gate count for the realization of sub field operations in the composite field GF ((22)2) compared to the GF (24) field. In the PRESENT lightweight cipher structure with the basic loop architecture, the proposed S-box demonstrates 5% reduction in the gate equivalent area over the look-up-table-based S-box with TSMC 180 nm technology.

Programmable Cellular Automata-Based Low-Power Architecture to S-Box : An Application to WBAN

In this paper, we presented a low-power, less area architecture of S-Box used in advanced encryption standard (AES) using programmable cellular automata (PCA). The proposed architecture performance in terms of security is evaluated using cryptographic properties such as nonlinearity, input/output entropy, correlation immunity bias, balancedness property, strict avalanche criterion, and it is found that the proposed method is secure enough for cryptography applications. The proposed architecture of AES with PCA-based S-Box is implemented on ASIC using TSMC 0.18-\({\upmu }\)m and UMC 0.13-\({\upmu }\)m CMOS technology libraries. Simulation studies show that the proposed architecture has average energy consumption of 58.702 nJ, power dissipation of 3.259 mW, area of 0.184 mm\(^2\), for TSMC 0.18-\({\upmu }\)m at 13.69 MHz and energy consumption of 18.275 nJ, power dissipation of 1.026 mW, area of 0.069 \({\upmu m}^{2}\) for UMC 0.13-\({\upmu }\)m at 13.69 MHz. The proposed architecture shows reduction in power dissipation by 83% and in energy consumption by 10% compared to the best classical S-Box and composite field arithmetic-based S-Box for AES algorithm. The S-Box using PCA is more flexible and dynamic in nature with low power, lesser energy consumption area and hence suitable for wireless body area network applications.

A new compact hardware architecture of S-Box for block ciphers AES and SM4

A new compact hardware architecture of S-Box for block ciphers AES and SM4

Low Power S-Box Architecture for AES Algorithm using Programmable Second Order Reversible Cellular Automata: An Application to WBAN

In this paper, we presented a novel approach of low energy consumption architecture of S-Box used in Advanced Encryption Standard (AES) algorithm using programmable second order reversible cellular automata (RCA 2). The architecture entails a low power implementation with minimal delay overhead and the performance of proposed RCA 2 based S-Box in terms of security is evaluated using the cryptographic properties such as nonlinearity, correlation immunity bias, strict avalanche criteria, entropy and also found that the proposed architecture is secure enough for cryptographic applications. Moreover, the proposed AES algorithm architecture simulation studies show that energy consumption of 68.726 nJ, power dissipation of 3.856 mW for 0.18- μm at 13.69 MHz and energy consumption of 29.408 nJ, power dissipation of 1.65 mW for 0.13- μm at 13.69 MHz. The proposed AES algorithm with RCA 2 based S-Box shows a reduction power consumption by 50 % and energy consumption by 5 % compared to best classical S-Box and composite field arithmetic based AES algorithm. Apart from that, it is also shown that RCA 2 based S-Boxes are dynamic in nature, invertible, low power dissipation compared to that of LUT based S-Box and hence suitable for Wireless Body Area Network (WBAN) applications.

A Novel Byte-Substitution Architecture for the AES Cryptosystem.

The performance of Advanced Encryption Standard (AES) mainly depends on speed, area and power. The S-box represents an important factor that affects the performance of AES on each of these factors. A number of techniques have been presented in the literature, which have attempted to improve the performance of the S-box byte-substitution. This paper proposes a new S-box architecture, defining it as ultra low power, robustly parallel and highly efficient in terms of area. The architecture is discussed for both CMOS and FPGA platforms, and the pipelined architecture of the proposed S-box is presented for further time savings and higher throughput along with higher hardware resources utilization. A performance analysis and comparison of the proposed architecture is also conducted with those achieved by the existing techniques. The results of the comparison verify the outperformance of the proposed architecture in terms of power, delay and size.

Incorporation of Wave Pipelined Techniques into Composite S-Box and AES Architectures

Advanced Encryption Standard is one of the most successful techniques used in various security applications. The AES technique is known to provide reliable security standards, which is why it is preferred over many other methods. The AES architecture consists of S-Box, Shift-Rows, Mix-Columns and Add Round key. Improving the S-Box structure using pipelining improves the speed of operations along with the security. The main aim of this research study is to design a modified composite S-Box for low area, power and high Speed with high security for application in AES process. In this study, we propose a WPT in S-Box also controlling the registers with a clock-gate structure, to further reduce the operational delay and obtain high security. The modified S-Box is then included in the AES architecture with an additional modification on the overall AES architecture by introducing the WPT in every round of AES operation. This is not only improves the speed of operation and also it provides high security compared to many existing techniques along with the area and power reduction. Simulations have been performed in the ModelSim6.3c and Synthesis is carried out using Xilinx10.1.

A Highly Parallel Area Efficient S-Box Architecture for AES Byte-Substitution

The performance of the S-Box represents an important factor in the overall performance of the AES cryptography systems. It affects the speed, area, and the power consumption of the AES. In attempts to improve the performance of the S-box byte substitution a number of techniques were presented in the literature. In this paper, we classify the S-box byte substitution optimization techniques as those based on hardware, software, and combined hardware/software. We then move on to propose a new highly parallel and area-efficient S-box architecture for AES byte substitution. We also conduct a performance analysis and comparison of the proposed architecture with those achieved by existing techniques. The comparison shows that the proposed architecture outperforms the existing techniques in terms of speed and area.

A Low Power Design of SM4 Cipher Based on MUX S-Box Architecture

SM4 is a 128-bit block cipher used in SOC and smart cards to ensure the safety of data transmission. In order to realize a low power implementation of the SM4 cipher block, some S-boxes were evaluated firstly and we proposed a new architecture of SM4 S-box called MUX S-box with a power consumption of 13.92W@10Mhz on SMIC 0.18m technology, Meanwhile, the implementation of SM4 cipher round based on the SM4 MUX S-box was completed and a low power consumption of 0.33mW @ 10 MHz on 0.18 m CMOS technology is achieved.

Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory

A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. We implement the AES in hardware because the hardware implementation has the advantage of increased throughput and offers better security. In order to reduce the constraint on the hardware resources while implementing the look-up table based s-box we propose a search based s-box architecture. Also the pipelined architecture of the AES algorithm is used in order to increase the throughput of the algorithm. The key schedule algorithm of the AES encryption is also pipelined.

Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory

A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.

On the S-Box Architectures with Concurrent Error Detection for the Advanced Encryption Standard

In this paper, we present a new low-cost concurrent error detection (CED) S-Box architecture for the Advanced Encryption Standard (AES). Because the complexity and the nonlinearity, it is difficult to develop error detection algorithms for the S-Box. Conventionally, a parity checked S-Box is implemented with ROM (read only memory). In some applications, for example, smart cards, both chip size and fault detection are demanded seriously. ROM-based parity checking cannot meet the demands. We propose our CED S-Box (CEDSB) architecture for two reasons. The first is to design a S-Box without ROM. The second is to obtain a compact S-Box with real time error detection. Based on the composite field, we develop the CEDSB architecture to implement the fault detection for the S-Box. The overhead of the CED for the S-Boxes in GF((24)2) and in GF(((22)2)2) are 152 and 132 NAND gates respectively. The amount of extra gates used for the CEDSB is nearly equal to that of the ROM-based CED S-Box (131 NAND gates). The chip area of the ROM-based CED S-Box, the CEDSBs in GF((24)2), and in GF(((22)2)2) are 2996, 558, and 492 NAND gates separately. The chip area of the CEDSB is more compact than a ROM-based CED S-Box.