VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

You-Tun Teng,Pin-Wei Chen,Deng-Kai Chang,Pei-Yin Chen,Wen-Long Chin

doi:10.1109/access.2021.3139040

You-Tun Teng, Pin-Wei Chen + Show 3 more

Open Access

https://doi.org/10.1109/access.2021.3139040

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Abstract

This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$((2^{2})^{2})$ </tex-math></inline-formula> , is reduced. The squaring and multiplication with constant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> in GF <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$((2^{2})^{2})$ </tex-math></inline-formula> are combined and optimized as well. Moreover, the multiplicative inversion in GF <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$((2^{2})^{2})$ </tex-math></inline-formula> is manually optimized. Furthermore, the S-box and inverse S-box are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.

Highlights

IntroductionCompared to the software solution [3], the hardware implementation is more suitable for high-throughput data applications
I N 2001, National Institute of Standard and Technology (NIST) invited proposals for new algorithm of the advanced encryption standard (AES) to replace the old data encryption standard (DES)
Compared to the software solution [3], the hardware implementation is more suitable for high-throughput data applications

Summary

Introduction

Compared to the software solution [3], the hardware implementation is more suitable for high-throughput data applications. The works [7]– [11] studied low-area implementations based on the fully combinational logic. The work [12] presented a S-box based on the multiplexer. The work [13] evaluated 5-, 6-, and 7-stages pipelined S-box based on the CFA. The studies, [14] and [15], proposed a 4-stage pipelined S-box. The study [18] proposed a new compact S-box. In [19], a joint AES encryption/decryption with a 7stage pipeline using the CFA was proposed. The study [20] proposed a parallel pipelined architecture to obtain high data throughput. The work [22] shared the circuitry of AES and

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