Phase-locked Loop Architecture Research Articles

A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning

This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL) architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to 6.1 GHz. The first and second loops, automatic frequency control (AFC) and counter-assisted phase-locked loop (CAPLL), respectively, perform coarse locking, while the third loop employs a digital sub-sampling architecture without a frequency divider for fine locking. In this third loop, fractional-N frequency synthesis is achieved using a delta-sigma modulator (DSM) and digital-to-time converter (DTC). To minimize area, digital modules such as counters, comparators, and differentiators used in the AFC and CAPLL loops are reused. Furthermore, a moving average filter (MAF) is employed to reduce the frequency overlap ratio of the digitally controlled oscillator (DCO) between the second and third loops, ensuring stable loop switching. The total power consumption of the WBPLL varies with the frequency range, consuming between 8.8 mW at the WBPLL minimum output frequency of 1.9 GHz and 12.8 mW at the WBPLL maximum output frequency of 6.1 GHz, all at a 1.0 V supply. Implemented in a 28 nm CMOS process, the WBPLL occupies an area of 0.055 mm2.

Overcoming the relative bandwidth limitations of single VCO frequency synthesizers by implementing a novel PLL architecture

Abstract Frequency-modulated continuous-wave radar systems profit from increasing the absolute bandwidths of the generated frequency chirps to improve range resolution. As the relative bandwidth of SiGe-voltage-controlled oscillators (VCOs) is limited to about 80%, increasing the center frequency fundamentally or via frequency multiplication is the most direct way to increase that absolute bandwidth. However, as some applications require penetration depth, which dramatically decreases with frequency, other solutions are necessary. Therefore, state-of-the-art concepts rely on the down-conversion of generated frequency chirps via two separately stabilized frequency sources. This article implements a novel architecture, offering relative bandwidths of >100% within a single phase-locked loop (PLL). Therefore, two VCOs at different center frequencies are fed into a down-conversion mixer, whose output is directly stabilized via that PLL with one loop filter generating both tuning voltages. Those circuit blocks can be summarized as one equivalent VCO, offering a higher relative bandwidth and a significantly more linear tuning curve. Thereby, a solution to limited relative bandwidths with high VCO gain variation of single VCO synthesizers is offered while substantially reducing the hardware and implementation effort compared to the state-of-the-art.

A novel replica technique based dead zone free phase frequency detector and a self-cascode current-splitting charge pump for a low-spur low power phase-locked loop architecture

In a phase-locked loop (PLL), a high reset pulse width in the phase frequency detector (PFD) and current mismatches in the charge pump (CP) are the major contributors to a high reference spur in a clock. This paper presents a novel replica technique based dead zone free PFD to reduce the reset pulse and a self-cascode current-splitting CP to reduce current mismatch. The proposed PFD and CP are designed using the UMC 180 nm CMOS process. The proposed PFD achieves a reset pulse width of 113 ps. The CP is designed for a CP current of 100 μA. It has an output voltage range of 0.4 V–1.2 V, with a current mismatch of 1.3%. A PLL with the proposed PFD+CP achieves a reference spur that is 39.5% lower than the reference spur of the PLL with conventional PFD+CP. The proposed PFD+CP consumes 0.28 mW power in the locked stated. The layout area consumed by the proposed PFD+CP is 46 × 75 μm2.

The Impact of Phase-Locked Loop (PLL) Architecture on Sub-Synchronous Control Interactions (SSCI) for Direct-Driven Permanent Magnet Synchronous Generator (PMSG)-Based Type 4 Wind Farms

Electric vehicles (EVs) are a promising solution to reduce carbon dioxide (CO2) emissions, but this reduction depends on the fraction of renewable sources used to generate electricity. Wind energy is thus a vital candidate and has experienced a remarkable surge recently, establishing itself as a leading renewable power source worldwide. The research on Direct-Driven Permanent Magnet Synchronous Generator (PMSG)-based type 4 wind farms has indicated that the Phase-locked Loop (PLL) bandwidth significantly impacts Sub-Synchronous Resonance (SSR). However, the influence of PLL architecture on SSR remains unexplored and warrants investigation. Therefore, this paper investigates PLL architectural variations in PLL Loop Filter (LF) to understand their impact on SSR in type 4 wind farms. Specifically, an in-depth analysis of the Notch Filter (NF)-based enhanced PLL is conducted using eigenvalue analysis of the admittance model of a PMSG-based type 4 wind farm. The findings demonstrate that the NF-based enhanced PLL exhibits superior performance and improved passivity in the sub-synchronous frequency range, limiting the risk of SSR below 20 Hz. Additionally, Nyquist plots are employed to assess the impact on system stability resulting in increased stability margins. In the future, it is recommended to further investigate and optimize the PLL to mitigate SSR in wind farms.

Stability Analysis for Fast Settling Switched Digital Phase-Locked Loops (DPLLs)

In current generation digital phase-locked loop (DPLL) architectures, techniques like gear-shift mechanism and switched phase-detection are employed to achieve better lock time and jitter performance. This work presents a framework for detailed analysis of the stability and settling behaviour of switched DPLL architectures using Lyapunov theory. The loop-parameters verified based on these stability conditions ensure that chattering does not occur during switching between different subsystems. A 5 GHz DPLL designed with these loop parameters and an error-tracking finite state machine (ET-FSM) is presented in this work. The state machine with a bang-bang phase detector (BBPD) aids in faster locking by tracking the settling behaviour of the loop in the previous clock cycles, and accordingly deciding the loop parameters. The DPLL with lock in around 100 clock cycles for 100 MHz reference clock, obtained using MATLAB and schematic simulations, verifies the efficacy of the state machine.

Performance Analysis of a RTK Vector Phase-Locked Loop Architecture for GPS Signal Tracking in Degraded Environments

Performance Analysis of a RTK Vector Phase-Locked Loop Architecture for GPS Signal Tracking in Degraded Environments

A system-level method for hardening phase-locked loop to single-event effects

To mitigate the sensitivity of the charge pump in a traditional Phase-Locked Loop(PLL), a single-event-hardened PLL architecture with a proportional and integral path is proposed. The phase margin of the PLL is kept at 58.16° due to the rational design and the output clock frequency ranges from 0.8 to 3.2 GHz. The circuit-level simulation results reveal that the sensitive volume of the hardened PLL decreases by 80% ∼ 95%. The novel radiation-hardened PLL circuit was implemented in a 28 nm CMOS technology and irradiated with heavy ions with a linear energy transfer between 1.9 and 65.6 MeV•cm2 mg−1. The proposed radiation-hardened PLL shows one order of single-event effects hardness level higher than the conventional PLL.

An Investigation of Grid Stability and a New Design of Adaptive Phase-Locked Loop for Wind-Integrated Weak Power Grid

This work investigates the impact of phase-locked loop (PLL) parameters on the stability of a wind-integrated weak power grid. The analysis is based on a weak grid model that integrates a Type-4 wind turbine generator with the grid represented by a lumped group model of a thermal power station with a steam governor and exciter system through a variable impedance network. This model is classically used for a weak grid study representing a real-life system. First, the impact of proportional and integral gain constants of the PLL on stability and oscillation characteristics is discussed in detail. Based on the analysis, an adaptive gain scheduling PI-based PLL architecture is proposed. The advantages of the proposed architecture are studied based on rigorous changes in the grid impedances and the wind dynamics. The results show that the proposed architecture significantly improves grid stability and damping when compared with conventional PLL designs.

A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications

This article presents a 23.9–29.4 GHz digital <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -phase-locked loop (PLL) architecture with a low phase noise (PN) and power-efficient coupled frequency doubler for 224 Gb/s PAM-4 transmitter clocking. The proposed frequency doubler is designed with two oscillators running at 14 and 28 GHz which are coupled by a transformer. Compared to a conventional frequency doubler or a two-way coupled oscillator, the coupling between the 14 and 28 GHz oscillators provides extra PN reduction as the 14 GHz oscillator can achieve lower PN than the 28 GHz one. In addition, by stacking the two oscillators through the transformer, the current is reused and hence power consumption is reduced. To optimize the PN performance across process, voltage, and temperature (PVT), a compact and power-efficient frequency-tracking loop (FTL) is implemented. The 14 GHz oscillator output is fed to the PLL feedback divider rather than the doubled output, which enables power saving in the prescaler divider in the feedback path. The proposed PLL is fabricated in 10 nm FinFET technology and the PLL achieves a 65 fs random jitter at the transmitter output after a 1st-order 4 MHz-BW CDR filtering which enables the industry’s first 224 Gb/s PAM-4 transmitter. Compared with a reference NMOS-GM <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -digitally controlled oscillator (DCO) implemented on the same die, the proposed coupled frequency doubler achieves 4.75 dB lower PN with only a 25% power consumption increase. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -PLL consumes 17.1 mW from a 0.8/1.0 V regulated supply and occupies an area of 0.088 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A fractional‐N MASH2‐k FDC phase‐locked loop architecture enabling higher‐order quantisation noise shaping

The quantisation noise contribution of a conventional FDC phase-locked loop (PLL) is still high due to the only second-order noise-shaping capability. A MASH2-k FDC PLL architecture enabling (k + 2)th-order noise shaping for more flexible loop design optimization and for a wider loop bandwidth to suppress the noise from the digitally controlled oscillator is proposed. The linear loop model is derived, and the noise contributions are analysed. The proposed PLL is evaluated with behavioural simulation whose results are consistent with those of the analysis. The results also suggest a lower phase noise of the proposed PLL compared with the conventional one.

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most powerful indicator to compare and to normalize performance of different PLL designs. Simply, the conventional FOM is based on the jitter-power trade-off. With a few assumptions, theoretically, it provides a fair comparison. However, as the PLL design techniques have advanced, the assumptions have started breaking. Also, it misses performance impacts from some other important factors other than the jitter and the power. As a result, it is expected that the performance comparison with the conventional FOM is not fair enough for some cases. This work reviews the state-of-the-art PLL design techniques and investigates how those techniques conflict with the assumptions of the conventional FOM. In addition, alternate FOMs which complement the conventional FOM are discussed. To capture complex cross-correlation between various factors, the proposed methodology is to find a correlation between the conventional FOM and other factors from extensive performance surveys, along with quantitative analyses.

A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To achieve ultra-low jitter in fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> mode, a phase detector range reduction technique is used to halve the required DTC delay range (DR), resulting in lower thermal noise and better DTC linearity. Moreover, a reconfigurable dual-core voltage-controlled oscillator (VCO) provides extra freedom in power and jitter tradeoff. It achieves 83.4-fs rms jitter in fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> mode, integrated from 10 kHz to 100 MHz, with a 76.8-MHz crystal oscillator (XO) reference. In the low-power mode, the rms jitter degrades to 96.3 fs and the PLL FoM improves from &#x2212;250.1 to &#x2212;251.2 dB, as the PLL power consumption reduces from 14.2 to 8.2 mW. The measured fractional spurs are less than &#x2212;70 dBc for near-integer channels. The PLL rms jitter remains within 100 fs across the 5&#x2013;7-GHz output frequency band, thanks to the digital background calibrations. It is implemented in a 14-nm FINFET process and occupies 0.31 mm².

Design and Implementation of High Frequency and Low-Power Phase-locked Loop

Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.

PFD with improved average gain and minimal blind zone combined with lock-in detection for fast settling PLLs

In this paper, two Phase frequency detector (PFD) architectures and a PFD with lock-in detection (PFD-LID) are proposed that are designed using the new techniques for selectively resetting the outputs to achieve improved average gain with a lower blind zone. The two proposed PFDs are designed and fabricated using 180 nm CMOS process. The circuits are tested with the variations in the supply voltage from 1.3 V to 1.8 V, achieving higher average gain and the measured blind zone of 3 ps, which is around five times less than earlier reported works. Also, the proposed selective reset techniques are used to design the PFD-LID. Both the PFDs and PFD-LID are validated using the traditional phase-locked loop (PLL) architecture by achieving minimal settling time of the PLL.

A 33 MHz Fast-Locking PLL with Programmable VCO and Automatic Band Selection for Clock Generator Application

This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO) gain stage with automatic band selection. We successfully reduce the VCO gain (Kvco) and retain the desired frequency band. The proposed PLL comprises a prescaler, phase frequency detector (PFD), charge pump (CP), programmable VCO and automatic band selection circuit. The PLL prototype with all subblocks was implemented using the TSMC 0.18 μm 1P6M process. Contrary to conventional PLL architectures, the proposed architecture incorporates a real-time check and automatic band selection circuit in the secondary loop. A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit. A suitable way to maintain the Kvco low is to use multiple discrete frequency bands to accommodate the required frequency range. To maintain a low Kvco and fast locking, the automatic frequency band selection circuit also has two indigenous, most probable voltage levels. The proposed architecture provides the flexibility of not only band hopping but also band twisting to obtain an optimized Kvco for the desired output range, with the minimum jitter and spurs. The proposed programmable VCO was designed using a voltage-to-current-converter circuit and current DAC followed by a four-stage differential ring oscillator with a cross-coupled pair. The VCO frequency output range is 150–400 MHz, while the input frequency is 25 MHz. A sequential phase detection loop with a negligible dead zone was designed to adjust fine phase errors between the reference and feedback clocks. All circuit blocks of the proposed PLL were simulated using the EDA tool HSPICE and layout generation by Laker. The simulation and measured results of the proposed PLL show high linearity, with a dead zone of less than 10 pV. The differential VCO was used to improve the linearity and phase noise of the PLL. The chip measured results show rms jitter of 19.10 ps. The PLL prototype also has an additional safety feature of a power down mode. The automatic band selection PLL has good immunity for possible frequency drifting due to temperature, process and supply voltage variations. The proposed PLL is designed for −40 to +85 °C, a wide temperature range.

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of -247dB, and normalized TR and area (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TA</sub> ) of -262dB.

A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC

In the present work, an all digital phase locked loop architecture (ADPLL) employing a bang-bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter (TDC) is designed to enhance the jitter and locking time performance. The proposed ADPLL utilizes a low power and high resolution 3-bit flash TDC with foreground calibration to suppress the issues of process, voltage and temperature (PVT) spreads and achieves low jitter and low power ADPLL. To obtain the fast locking, a proposed dynamic bang-bang PFD is used. The proposed ADPLL takes only 5 iterations to achieve the locking from unlocked state. Additionally, ADPLL employs a wide range and low phase noise voltage controlled oscillator (VCO) based on inverters to obtain a reduced jitter in ADPLL. The proposed ADPLL is designed in 180-nm SCL digital CMOS technology at 1.8 V supply. It consumes a total power of 5.94 mW at 1.8 V. From the post layout simulations, the achieved FoM and periodic jitter is −227.6 dB and 1.71 ps respectively at an output frequency of 1.6 GHz. The achieved phase noise of proposed ADPLL is −131.2 dBc/Hz at offset of 100 MHz.

A Dividerless Ring Oscillator PLL With 250fs Integrated Jitter Using Sampled Lowpass Filter

This brief presents a novel ring oscillator based phase lock loop architecture that is capable of wideband, dividerless integer-N synthesis. The noise transfer function of the presented architecture is the same as a sub-sampling phase lock loop (PLL). Like a sub-sampling PLL, the presented architecture removes the phase detector and charge pump’s $N^{2}$ noise that dominates the in-band noise of traditional PLLs. This noise reduction allows the presented ring oscillator PLL to operate with integrated jitter as low as 250fs. Unlike sub-sampling PLLs, the presented architecture moves the sampling block downstream of the loop filter. As the sampled data is lowpass filtered, only low frequency sampling blocks are required, which removes the power and area overheads associated with directly sampling the voltage controlled oscillator. Measurement results show the presented PLL is capable of locking over a wide range of 1.2-2.5GHz. The presented PLL is fabricated in 65nm bulk CMOS, and demonstrates a figure of merit of −242.7dB, which is among best in class for ring oscillator PLLs. Furthermore, an area of 0.0066 mm2 is consumed, which represents the smallest published sub-sampling ring oscillator PLLs.

Smoothing the Way for Digital Phase-Locked Loops: Clock Generation in the Future with Digital Signal Processing for Mitigating Spur and Interference

Phase-locked loops (PLLs) are widely deployed in most electronic systems to generate a desired clock frequency, perform clock data recovery (CDR), and achieve frequency or phase modulation depending on the intended applications, such as Wi-Fi, Bluetooth, 5G, gigabit Ethernet, or optical fiber communication. Recently, the trend toward system-on-chip (SoC) has resulted in the need for a low-cost, robust, and highly reconfigurable PLL architecture [1], [3]?[8], [11], [13]?[22], [28]?[30], [32], [35]. This large-scale integration for advanced application requires a deeply scaled, integrated circuit technology with a low supply voltage, but it inevitably results in a design bottleneck, such as voltage headroom or reliability issues, for analog PLLs. Hence, interest in a digital PLL (DPLL) architecture has increased as its digital nature offers the advantage of technology scaling in a way that analog PLLs do not. In addition, the DPLL architecture is more flexible and reduces area and power consumption because its compact digital logics replace bulky and passive analog components.

A 28-nm 75-fsrms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

An analog fractional- $N$ sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- $N$ mode with a 52-MHz reference clock. The measured fractional spur is less than −64 dBc across the 5.5–7.3-GHz output frequency band. The PLL employs digital-to-time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur. This design meets the performance requirement of the 5G cellular 64-quadratic-amplitude modulation (QAM) standard in the 28-/39-GHz band, supporting $2 \times 2$ multi-in multi-out (MIMO). This paper, implemented in a 28-nm CMOS process, is integrated in a 5G millimeter-wave cellular transceiver. This PLL consumes 18.9 mW and occupies 0.45 mm2.