Computer System Architecture Research Articles

The impact of data flow computing thinking on the development of computer architecture

Throughout the entire history of computer architecture, the von Neumann model has been the most mainstream model for computer systems architecture. Data flow computer systems are undoubtedly the most well-studied type of non-von Neumann computer architecture. In this paper, from the perspective of the computer architecture development, we analyze the important role that data flow computing thinking has played in both innovation in computer architecture and in the development of computer architecture over time. We first review the thinking behind data flow computing and analyze the limitations it faced in its early stages. Then we analyze two important technologies used in modern CPUs-out-of-order execution and multi-threading technology-that were both developed using data flow computing thinking. We continue to view streaming computing, streaming processor architecture, and modern GPUs through the lens of data flow computing thinking. Further, we analyze how to apply data flow computing thinking to the development of computer systems in the era of big data intelligence. Finally, we summarize the rules of data flow computing thinking and forecast future development trends.

On planar self-folding magnetic chains: Comparison of Newton–Euler dynamics and internal energy optimisation

Within the wide field of self-assembly, the self-folding chain has the unique capability to pass through narrow openings, too small for the assembled structure, yet consists in one connected body. This paper presents a novel analytical framework and corresponding experimental setup to quantify the results of a self-folding process using magnetic forces at the centimetre-scale, with the aim to put experimental results and prediction methods in the context of surgical anchoring and therapy. Two possibilities to predict the folding of a chain of magnetic components in 2D are compared and investigated in an experimental setup. Folding prediction by system Coulomb energy, neglecting folding dynamics, is compared with a simulation of the system dynamics using a novel approach for 2D folding chains, derived from the Newton–Euler equations. The presented algorithm is designed for the parallel computation architecture of modern computer systems to be easily applicable and to achieve an improved simulation speed. The experimental setup for the self-folding chain used to validate the simulation results consists of a chain of magnetic components where movement is limited to one plane and the chain is agitated by the magnetic forces between the chain components. The folding process of the experimental setup is validated for its stability and predictability under different deployment modes. Finally, the results are discussed in light of the folding prediction of longer chains. The implications of the presented findings for a 3D folding chain are discussed together with the challenges to apply the novel dynamics simulation algorithm to the 3D case. The work clearly demonstrates the potential for this novel approach for complex self-folding applications such as magnetic compression anastomosis and anchoring in minimally invasive surgery.

Performance Reduction for Automatic Development of Parallel Applications for Reconfigurable Computer Systems

In the paper, we review a suboptimal methodology of mapping of a task information graph on the architecture of a reconfigurable computer system. Using performance reduction methods, we can solve computational problems which need hardware costs exceeding the available hardware resource. We proved theorems, concerning properties of sequential reductions. In our case, we have the following types of reduction such as the reduction by number of basic subgraphs, by number of computing devices, and by data width. On the base of the proved theorems and corollaries, we developed the methodology of reduction transformations of a task information graph for its automatic adaptation to the architecture of a reconfigurable computer system. We estimated the maximum number of transformations, which, according to the suggested methodology, are needed for balanced reduction of the performance and hardware costs of applications for reconfigurable computer systems.

Integrated Analysis of Performance and Resources in Large-Scale Quantum Computing

To see the feasibility of a large-scale quantum computing, it is required to accurately analyze the performance and the quantum resource. However, most of the analysis reported so far have focused on the statistical examination, i.e., simply calculating the performance and resource based on individual data, and even worse usually only a few components have been considered. In this work, to achieve more exact analysis, we propose an integrated analysis method for a practical quantum computing model with three components (\textit{algorithm}, \textit{error correction} and \textit{device}) under a realistic quantum computer system architecture. To implement the above method, we develop a quantum computing framework composed of three functional layers: compile, system and building block. This framework can support, for the first time, the mapping of quantum algorithm from physical qubit level to system architecture level with a given fault-tolerant scheme. Therefore, the proposed method can measure the effect of dynamic situation when the quantum computer practically runs. By using our method, we found that Shor algorithm to factorize 512-bit integer requires $8.78\times 10^ 5$ hours. We also show how the proposed method can be used for analyzing optimal concatenation level and code distance of fault-tolerant quantum computing.

Chaotic Architectures: a New Trend in Computers

Information technologies are analyzed and their components are identified as virtualization technologies, quantitative technologies, data technologies, and knowledge technologies. Based on the analysis, it is determined that chaotic architectures of computer systems are a new trend in the development of these systems.

Multi-GPU, Multi-Node Algorithms for Acceleration of Image Reconstruction in 3D Electrical Capacitance Tomography in Heterogeneous Distributed System.

Electrical capacitance tomography (ECT) is one of non-invasive visualization techniques which can be used for industrial process monitoring. However, acquiring images trough 3D ECT often requires performing time consuming complex computations on large size matrices. Therefore, a new parallel approach for 3D ECT image reconstruction is proposed, which is based on application of multi-GPU, multi-node algorithms in heterogeneous distributed system. This solution allows to speed up the required data processing. Distributed measurement system with a new framework for parallel computing and a special plugin dedicated to ECT are presented in the paper. Computing system architecture and its main features are described. Both data distribution as well as transmission between the computing nodes are discussed. System performance was measured using LBP and the Landweber’s reconstruction algorithms which were implemented as a part of the ECT plugin. Application of the framework with a new network communication layer reduced data transfer times significantly and improved the overall system efficiency.

The Computer System Architecture of our first real-time real-world experiment of adaptive traffic signals with "connected" vehicles

Connected vehicles can transmit real-time information to traffic control management systems. Despite the recent technical advances of telecommunication networks and mobile computing there have been no real-time adaptive traffic signal control experiments with connected vehicles. Most of the research in this field has been carried out only with simulations. In this work we present the computer system that was adopted to regulate traffic signals in real-time with "smartphone-connected" vehicles as the only source of information. We introduce the description of the computer system architecture that was deployed in an experiment of a Floating Car Data (FCD)-based adaptive traffic signal in which a traffic signal has been regulated in real-time with 100% "smartphone-connected" vehicles. The description of the system based on commonly-used technologies could help others to develop and deploy new traffic signal management systems in new "connected" intersections.

CPU–GPU Utilization Aware Energy-Efficient Scheduling Algorithm on Heterogeneous Computing Systems

Nowadays, heterogeneous computing systems have proven to be a good solution for processing computation intensive high-performance applications. The main challenges for such large-scale systems are energy consumption, computing node CPU-GPU utilization dynamic variability, and so on. In response to these challenges, this study first provides heterogeneous computing systems architecture and parallel application job model. Then, we build system computing node CPU-GPU utilization model and analyze job execution energy consumption. We also deduce the optimal CPU-GPU utilization and job deadline scheduling constraint. Third, we propose a systems CPU-GPU utilization aware and energy-efficient heuristic greedy strategy (UEJS) to solve this job scheduling problem. To improve the algorithm global optimization ability, we design a hybrid particle swarm optimization algorithm (H-PSO), which incorporates the heuristic greedy strategy into the bio-inspired search optimization technique. The rigorous experimental results clearly demonstrate that our proposed H-PSO outperforms heuristic greedy strategy, Max-EAMin, and Genetic Algorithm in terms of the average energy consumption of jobs and system job rejection rate. In particular, H-PSO is better than UEJS by 36.5%, Max-EAMin by 36.3%, and GA by 46.7% in term of the job average energy consumption for heterogeneous system with high workload.

Design of loading test bench for precision ball screw based on LabVIEW+PXI

In order to discuss the dynamic characteristics of the aerospace ball screw pair, the paper designs a loading test bench based on Labview+PXI platform and magnetic powder brake. The test bench can simulate the loading condition up to 10Hz. In structural design, magnetic powder brake is used to apply the loading force. In hardware design, the system is built by using upper-lower computer system architecture based on PXI bus. In software design, the program is written in LabVIEW, which mainly includes the data processing and display program in the upper computer and the data acquisition program, the motor control program in the lower computer (PXI). Finally, the test bench was built and the inertia loading test and the rated speed loading test were carried out. The test results verify the effectiveness of the high-frequency loading measurement and control system, and provide a reliable test platform for the dynamic characteristics of the ball screw pair under high-frequency conditions.

Hierarchical Load Balancing and Clustering Technique for Home Edge Computing

The edge computing system attracts much more attention and is expected to satisfy ultra-low response time required by emerging IoT applications. Nevertheless, as there were problems on latency such as the emerging traffic requiring very sensitive delay, a new Edge Computing system architecture, namely Home Edge Computing (HEC) supporting these real-time applications has been proposed. HEC is a three-layer architecture made up of HEC servers, which are very close to users, Multi-access Edge Computing (MEC) servers and the central cloud. This paper proposes a solution to solve the problems of latency on HEC servers caused by their limited resources. The increase in the traffic rate creates a long queue on these servers, i.e., a raise in the processing time (delay) for requests. By leveraging, based on clustering and load balancing techniques, we propose a new technique called HEC-Clustering Balance. It allows us to distribute the requests hierarchically on the HEC clusters and another focus of the architecture to avoid congestion on a HEC server to reduce the latency. The results show that HEC-Clustering Balance is more efficient than baseline clustering and load balancing techniques. Thus, compared to the HEC architecture, we reduce the processing time on the HEC servers to 19% and 73% respectively on two experimental scenarios.

CamCutter: Impromptu Vision-Based Cross-Device Application Sharing

AbstractAs the range of handheld, mobile and desktop devices expands and worldwide demand for collaborative application tools increases, there is a growing need for higher speed impromptu cross-device application sharing to keep up with workplace requirements for on-site or remote collaborations. To address this, we have developed CamCutter, a cross-device interaction technique enabling a user to quickly select and share an application running on another screen using the camera of a handheld device. This technique can accurately identify the targeted application on a display using our adapted computer vision algorithm, system architecture and software implementation, allowing impromptu real-time and synchronized application sharing between devices. For desktop and meeting room set-ups, we performed a technical evaluation, measuring accuracy and speed of migration. For a single-user reading task and a collaborative composition task, we carried out a user study comparing our technique with commercial screen sharing applications. The results of this study showed both higher performance and preference for our system. Finally, we discuss CamCutter’s limitations and present insights for future vision-based cross-device application sharing.

Stateful Three-Input Logic with Memristive Switches

Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation.

TECHNIQUE OF REDUCTION TRANSFORMATIONS FOR MINIMIZATION OF ANALYZED NUMBER OF PARALLEL PROGRAM VARIANTS

Formulated several important conclusions of the basic theorems and the main principles of the reduction transformations’ technique. In comparison with automatic parallelizing, the proposed principles provide a considerable decrease in the number of steps required for the applications’ adaptation to architectures of reconfigurable computer systems. At the first stage, the reduction coefficient is factorized, and the rational values of different types of reduction coefficients (by the number of basic subgraphs, by the number of computational operations and by the digit capacity of data) are chosen from the multipliers. At the second stage, the reduction of basic subgraphs’ number is performed according to the coefficient chosen at the previous stage. At the third stage, the number of computational operations and the digit capacity of processed data are reduced to the limit values. The application of the reduction transformations’ technique allows for the integration of multiple variants of parallel program in one group and for the shortening of time needed for its adaptation to the architecture and configuration of a computer system. According to the estimations, the number of reduction transformation steps needed for the calculations’ scaling in reconfigurable computer systems is 26 steps and considerably less than the one for automatic parallelizing compilers.

Features of the Architecture Implementing the Dataflow Computational Model and Its Application in the Creation of Microelectronic High-Performance Computing Systems

At present, high-performance computations are in general use: in the government sector, defense sphere, large-scale concerns and enterprises, commercial entities, etc. From year-to-year, increasing sums are invested in supercomputers and software to rapidly answer any challenges in some field. In general, present-day high-performance computing systems are based on the von Neumann computation model. This, in turn, imposes certain restrictions, in particular, on paralleling computations and, as a consequence, on the creation of effective parallel applications. In this paper, one of the ways of solving this problem is proposed, namely, transition to the original dataflow computation model with a dynamically generated context and its implementation in a parallel dataflow computing system. Peculiarities of the parallel dataflow computing system architecture and the advantages offered by them are described. Such architectures will be in demand when creating new microelectronic high-performance computation systems.

Features of training 3d computer modeling and visualization of future teachers of informatics

The cognitive, developing, illustrative potential of three-dimensional computer graphics actualizes the training of future teachers in its technologies. The future teacher of computer science should be able to develop three-dimensional models and animations of the studied objects (phenomena and processes) in computer science, physics, mathematics and other academic disciplines, create copyright electronic educational resources with three-dimensional illustrations, apply augmented reality and 3D printing in professional activities.The article describes the features of teaching three-dimensional computer modeling and visualization of future informatics teachers, identified on the basis of an analysis of the training system for students studying in specialty 1–02 05 02 Physics and Informatics at the Maxim Tank Belarusian State Pedagogical University.The main directions for improving the learning process of three-dimensional computer graphics of future informatics teachers are indicated. Questions on three-dimensional computer modeling and visualization will pass through the content line through the content of six academic disciplines («Computer graphics and multimedia», «Computational methods and computer modeling», «Programming Technologies and Algorithmization Methods», «Information Technologies in Education», «Methods teaching informatics» and «Architecture and software of computer systems»). This will ensure consistency in the introduction and study of concepts, the choice of forms and methods of teaching, the development of teaching and methodical support. For the implementation of interdisciplinarity, it is proposed to carry out practice-oriented interdisciplinary educational projects in the framework of the study of academic disciplines in three subject areas «Computer Science», «Physics» and «Mathematics». The development of a methodical system of interdisciplinary education will ensure the formation of readiness to teach three-dimensional graphics at the stage of general secondary education and to realize its didactic possibilities in organizing educational and research activities of students.

Формування технічних умінь в системі професійної підготовки майбутніх фахівців з інформаційних технологій

В статті піднімається проблема практично-технічної підготовки майбутніх бакалаврів з комп’ютерних наук в контексті навчання основних курсів технічних дисциплін. Структура і зміст професійної діяльності розглядається через технічну складову проектних вмінь, що відображені в освітньо-кваліфікаційних документах підготовки бакалаврів, магістрів. Визначені напрямки методологічної діяльності зі створення моделі навчання шляхом трансформації технічних знань в систему проектних вмінь. Показано, що навчання циклу, таких технічних дисциплін, як «теорія електричних та магнітних кіл», «комп’ютерна схемотехніка», «архітектура комп’ютерних систем», «операційні системи», «комп’ютерні мережі», які входять до базису основного курсу підготовки бакалаврів з комп’ютерних наук і вивчаються студентами протягом не менше трьох семестрів, має значний потенціал для послідовного формування технічних умінь в процесі виконання творчих проектів.

The N3XT Approach to Energy-Efficient Abundant-Data Computing

The world’s appetite for analyzing massive amounts of structured and unstructured data has grown dramatically. The computational demands of these abundant-data applications, such as deep learning, far exceed the capabilities of today’s computing systems and are unlikely to be met with isolated improvements in transistor or memory technologies, or integrated circuit architectures alone. To achieve unprecedented functionality, speed, and energy efficiency, one must create transformative nanosystems whose architectures are based on the salient properties of the underlying nanotechnologies. Our Nano-Engineered Computing Systems Technology (N3XT) approach makes such nanosystems possible through new computing system architectures leveraging emerging device (logic and memory) nanotechnologies and their dense 3-D integration with fine-grained connectivity to immerse computing in memory and new logic devices (such as carbon nanotube field-effect transistors for implementing high-speed and low-energy logic circuits) as well as high-density nonvolatile memory (such as resistive memory), and amenable to ultradense (monolithic) 3-D integration of thin layers of logic and memory devices that are fabricated at low temperature. In addition, we explore the use of several device and integration technologies in the N3XT beyond the specific ones mentioned earlier that are also used in our main nanosystem prototypes. We also present an efficient resiliency technique to overcome endurance challenges in certain resistive memory technologies. N3XT hardware prototypes demonstrate the practicality of our architectures. We evaluate the benefits of the N3XT using a simulation framework calibrated using experimental measurements. System-level energy-delay product of common implementations of abundant-data workloads improves by three orders of magnitude in the N3XT compared with conventional architectures. These improvements impact a broad range of application workloads and architecture configurations, from embedded systems to the cloud.

Design of Electric Linear Load Simulator based on LabVIEW+PXI

In order to realize the hardware-in-the-loop (HIL) experiments of a certain type of electric linear actuator in the laboratory, an electric linear load simulator (ELLS) based on LabVIEW+PXI platform was developed to simulate the external force of the actuator under actual working conditions. In structural design, the ball screw is used to convert the PMSM torque into linear force. In hardware design, the system is built using the upper-lower computer system architecture based on PXI bus. In software design, the program is written in LabVIEW, which mainly includes the data processing and display program in the upper computer and the data acquisition program, the loading motor control program and the actuator control program in the lower computer (PXI), in order to ensure the loading accuracy of ELLS, control methods such as force closed-loop PID controller, position feedforward compensation and input feedforward compensation are also introduced in the loading motor program. Finally, the ELLS was built and the signal tracking tests were carried out. The experimental results shows that the loading accuracy can reach 93.5% and 90.3% when ELLS tracks 1000N-2 Hz and 1000N-5 Hz respectively, which proved that the accuracy of ELLS satisfies the “Double Ten Index”.

A Study of Mobile Edge Computing System Architecture for Connected Car Media Services on Highway

The new mobile edge network architecture has been required for an increasing amount of traffic, quality requirements, advanced driver assistance system for autonomous driving and new cloud computing demands on highway. This article proposes a hierarchical cloud computing architecture to enhance performance by using adaptive data load distribution for buses that play the role of edge computing server. A vehicular dynamic cloud is based on wireless architecture including Wireless Local Area Network and Long Term Evolution Advanced communication is used for data transmission between moving buses and cars. The main advantages of the proposed architecture include both a reduction of data loading for top layer cloud server and effective data distribution on traffic jam highway where moving vehicles require video on demand (VOD) services from server. Through the description of real environment based on NS-2 network simulation, we conducted experiments to validate the proposed new architecture. Moreover, we show the feasibility and effectiveness for the connected car media service on highway.

Simulation of Flying Parallel Modelling in Computer

The existence of types of mathematical models is conditioned by characteristics of the examined object. The process of synchronizing program modules employs this division in Information and Communication Technologies that are examined and optimized for the simulation process. The main problem in the process of synchronization is that how computing is done by the distributed control system – cluster or network. How can conditions of mathematical models be managed and how computing can become a creative and effective process. The physics of simulation model is well done and it is examined by their parameters easily. Now this model construction for some time is able to simulate the design of models very authentically. This work focuses on this very important field of science and technical community. The theory of design of decentralized computer control systems are derived from computers that create a distributed computer system of a flight simulator. Modelling of a time benefit of a simulator system is done by description using equations depending on architecture of computer systems. An important part of this article is the way of analysis types of mathematical models, a simulation method and an analytical approach, a corresponding calculation of a control implemented in single-processor architecture.