Discrete Wavelet Transform Architecture Research Articles

Low-Power, Low-Area Multi-level 2-D Discrete Wavelet Transform Architecture

This paper introduces an efficient, low-power, low-area multi-level 2-D discrete Haar wavelet transform (2-D DHWT) architecture. The proposed architecture consists of four add/subtract elements, register bank, three multiplexers and a buffer memory. All or fractions of the N-stage register are used to perform row–column image transposition for every 2-D DHWT decomposition level. A fixed size block memory of \(\frac{{{\varvec{N}}}}{{{\varvec{2}}}}\times \frac{{{\varvec{N}}}}{{{\varvec{2}}}}\)-sample is used to store low–low frequency band to perform multi-level 2-D DHWT decomposition, except for the first level where no block memory is used. For synthesis results, the proposed architecture outperforms similar architectures in hardware usage, power consumption and speed. Also, it is found that the power delay product of the proposed architecture is less than 1 \((\hbox {mW} \times \upmu \hbox {s})\) compared with up to 1.9 \((\hbox {mW} \times \upmu \hbox {s})\) for cascaded architecture. Furthermore, an up to 209 MHz processing speed is achieved which enables a three-level 2-D DHWT decomposition of a \(256\times 256\)-pixel image to be performed within 0.4 ms.

Novel one-dimensional and two-dimensional forward discrete wavelet transform 5/3 filter architectures for efficient hardware implementation

We implemented a more efficient circuit for one-dimensional (1-D) forward discrete wavelet transform (DWT) 5/3 filter. Our design utilizes processing and memory resources that are wasted in some other state-of-the-art solutions and is at least 33% simpler in terms of used registers, is 17% simpler in terms of used logic elements, has 7% higher maximum operating frequency and has 2% lower total power dissipation than previously published designs. The advantages of our design are achieved by a novel non-stationary filter topology which reuses the same registers for generating both low-pass and high-pass output coefficients, in different time slots, due to feed-forward and feedback paths. Our design is suitable for image compression systems which use 5/3 filter, e.g., JPEG 2000. We also proposed two-dimensional (2-D) DWT 5/3 architecture which uses implemented 1-D DWT filter design. The proposed 2-D DWT architecture outperforms all previously published architectures in terms of required memory capacity, which is at least 20% lower than memory capacity in any other reported solution.

VLSI Architectures for Lifting Based Discrete Wavelet Transform – A Survey

<p>Image compression is a key technology in the development of various multimedia and communication applications. Perfect reconstruction of the image without any loss in picture quality and data is very important. This can be achieved with the Discrete Wavelet Transform (DWT), which is an efficient tool for image compression and video compression. The lifting based DWT architecture has the advantage of lower computational complexities and also requires less memory compared to the conventional convolution method. The existing DWT architectures are represented in terms of folded, flipping and recursive structures. The various architectures are discussed in terms of memory, power consumption and operating frequency involved with the given size of image and required levels of decomposition. This paper presents a survey of these architectures for 2-dimensional and 3-dimensional Discrete Wavelet Transform. This study is useful for deriving an efficient method for improving the speed and hardware complexities of existing architectures.</p>

Design of Enhanced Half Ripple Carry Adder For VLSI Implementation Of Two-Dimensional Discrete Wavelet Transform

This paper presents a systematic high speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High- speed 2-D DWT with computation time as low as N2/12 can be easily achieved for an N X N image with controlled increase of hardware cost. Compared with recently published 2-D DWT architectures with computation time of N2/3 and 2N2/3, the proposed designs can also save a large amount of multipliers and/or storage elements. In proposed DWT models, adders are recognized as high potential than other components. In order to improve the efficiency of DWT process, an efficient adder called “Enhanced Half-Ripple Carry Adder (EHRCA)” has been designed in this research work. Proposed EHRCA circuit offers10.71% improvements in hardware slice utilization, 11.78% improvements in total power consumption than traditional Binary to Excess 1 Conversion (BEC) based Square Root Carry Select Adder (SQRT CSLA).

Memory-efficient high-speed VLSI implementation of multi-level discrete wavelet transform

Memory requirements and critical path are essential for 2-D Discrete Wavelet Transform (DWT). In this paper, we address this problem and develop a memory-efficient high-speed architecture for multi-level two-dimensional DWT. First, dual data scanning technique is first adopted in 2-D 9/7 DWT processing unit to perform lifting operations, which doubles the throughputs per cycle. Second, for 2-D DWT architecture, the proposed Row Transform Unit and Column Transform Unit take advantage of input sample availabilities and provision computing resources accordingly to optimize the processing speed, in which the number of processors is further optimized to significantly reduce the hardware cost. Third, to address the problem of high cost of memory for the immediate computing results from each level and the computation time as resolution level increases, multiple proposed 2-D DWT units were combined to build a parallel multi-level architecture, which can perform up to six levels of 2-D DWT in a resolution level parallel way on any arbitrary image size at competitive hardware cost. Experimental results demonstrated that the proposed scheme achieves improved hardware performance with significantly reduced on-chip memory resource and computational time, which outperforms the-state-of-the-art schemes and makes it desirable in memory-constrained real-time application systems.

Lifting-based Discrete Wavelet Transform for Real-Time Signal Detection

Background: Discrete Wavelet Transform (DWT) is extensively useful in different Digital Signal Processing (DSP) applications. In this paper, Lifting scheme is introduced in three mother wavelets, which are Haar wavelet, Daubechies (db4) and Cohen-Daubechies-Feauveau (CDF) 9/7-tap wavelet also known as db9/7 wavelet. Method: In this work each of the architecture is compared with its Direct form. Haar wavelet is used to design the basic DWT architecture. Daubechies DWT (db4) orthogonal filters and Cohen-Daubechies-Feauveau (CDF) 9/7 bi-orthogonal wavelet filters are considered for DWT construction. Due to the uncomplicated design, lifting scheme provides less power consumption. Instead of set of filters, simple predict and update mechanism is introduced. The IEEE 754 floating point standard is used to represent the filter coefficients. The architectures are described in Verilog HDL and simulation is performed in Xilinx for FPGA implementation. All the architectures are synthesized in Cadence RC for 180 nm technology. Findings: The Lifting Scheme has 75-82% less power consumption and 27% area-efficiency than conventional DWT architectures. FPGA implementation is done using Altera Cyclone IV FPGA kit. Maximum operating frequency is 33.3MHz and 45MHz for 3-level and 1-level of decomposition respectively in DWT implementation. Conclusion: Due to the uncomplicated design, lifting scheme provides less power consumption. DWT designs are compared with respect to power consumption and area.

Low Complexity DWT Architecture Implementation for Feature Extraction using Different Multipliers

Background/Objectives: Discrete wavelet Transform (DWT) is substantially applied in many Digital Signal Processing (DSP) applications. Multiplication of the coefficient is the key factor for complexity in FIR filters. Methods/Statistical Analysis: This paper presents different multiplication techniques used to reduce the complexity in DWT such as Constant Shift Method (CSM), Vedic multiplication and Binary Signed Sub-coefficient (BSS) method. CSM technique uses Shift and Add unit followed with Mux to select appropriate output. BSS technique uses signed sub-coefficients, which reduces the multiplexer size. Vedic multiplication is famous for its low complexity architecture of bit-bit multiplication. Partial product and BCSE methods are used for designing the architectures. The coefficients are represented in IEEE 754 floating point half precision standard. Software simulation is performed in ModelSim and the designs are synthesized in Cadence RC tool for 180 nm technology. Findings: The CSM method gives high speed operation because of its reduced number of adders. The Vedic method provides low power and high speed operation. The BSS method uses Multiplexers and signed bit as control switch, which has a great impact over area requirement. The area requirement is reduced by 6% in BSS technique. Vedic multiplier gives about 23% power reduction compared to conventional multiplier. Both CSM and BSS techniques can be called Reconfigurable architectures as they can be hardwired and the mux output depends on the coefficients only. Conclusion/Improvements: CSM technique is gives the perfect balance for power reduction and area efficiency. Vedic technique gives immense reduction in power consumption but the area overhead is increased.

English

Digital Signal processing ranks among the most demanding applications of digital design concepts. It is a mature technology domain wherein the demands for enhanced performance and resource utilization have risen exponentially over the years. Finite impulse response (FIR) filters are used in Digital Signal Processing applications.Accuracy in Filter Designing is based on the Multiplication and accumulation of filter coefficients. This paper describes an approach to the VLSI implementation of digital filter which is flexible and provides superior to traditional approaches,low power, and area efficient Discrete Wavelet Transform architecture.

Design and FPGA Implementation of Two-Dimensional Discrete Wavelet Transform Architectures Using Raster-Scan Method

Design and FPGA Implementation of Two-Dimensional Discrete Wavelet Transform Architectures Using Raster-Scan Method Jassim M. Abdul-Jabbar Zahraa Talal Abed Al-Mokhtar Dept. of Computer Eng., College of Eng., University of Mosul, Mosul, Iraq drjssm@gmail.com zah_ta84@yahoo.com Abstract In this paper, an FPGA implementation of a 2-dimenional discrete wavelet transform (2-D DWT) is proposed to efficiently construct the corresponding twodimensional architecture by using the raster-scan image method for any given hardware architecture of one dimensional (1-D) wavelet transform filter. The proposed method is based on lifting scheme architecture. The resulting architectures are simple, modular and regular for computation of one or multilevel 2-D DWT. These architectures perform both low pass and high pass filter with multiplierless coefficients calculation. In addition they require a small on-chip area to download the architectures on FPGA Board (Spartan-3E). The proposed 2-D architecture consists of: external memory, Row 1-D arithmetic module, column 1-D arithmetic module and internal memory unit. The row and column 1-D arithmetic units are designed utilizing Biorthogonal filters (5/3 and 9/7). Keywords: 2-D DWT, FPGA implementation, Lifting scheme architecture, Rasterscan method. للتحويل المويجي المتقطع ذي البعدين FPGA التصميم والتنفيذ باستخدام بطريقة المسح النقطي د. جاسم محمد عبد الجبار زهراء طلال عبد علي المختار قسم هندسة الحاسوب – كلية الهندسة - جامعة الموصل – الموصل - العراق zah_ta84@yahoo.com drjssm@gmail.com الخلاصة FPGA 2- ) بإستخدام D DWT( في هذه البحث، تم اقتراح تنفيذ بنية التحويل المويجي المتقطع ذي البعدين 1- (. وتستند D( بكفاءة من خلال أسلوب صورة المسح النقطي لأي بنية مادية للتحويل المويجي ذات البعد الواحد الطريقة المقترحة على معمارية مخطط الرفع. البنية الناتجة كانت بسيطة ونموذجية ومنتظمة لحساب مستوى واحد أو 2- )، هذه البنية يمكنها تنفيذ عمليات مرشح الإمرار D DWT) عدة مستويات من التحويل المويجي المتقطع ذي البعدين الواطيء ومرشح الإمرار العالي مع إجراء الحساب للمعاملات بدون مضارب. وبالإضافة إلى ذلك فإنها تتطلب مساحة يتكون الهيكل ذي البعدين المقترح من: الذاكرة الخارجية ووحدة .(Spartan-3E) نوع FPGA صغيرة على رقاقة حساب الصف ذات البعد الواحد ووحدة حساب العمود ذات البعد الواحد بالإضافة الى وحدة الذاكرة الداخلية ذات البعد 9) ثنائية التعامد.

A Multiplier-Less Lifting Scheme Based DWT Structure

The merits of Discrete Wavelet Transform (DWT) over other traditional transforms have led to tremendous focus on the applications of Wavelet Transforms. This leads to the requirement for developing a hardware efficient VLSI implementation of the DWT along with low power consumption. In this paper, DWT architecture based on lifting scheme is considered with suitable modifications to the architecture by adopting low power techniques, which contributes to hardware efficient and low power implementation. A shift-add multiplier with signed floating point consideration is used to construct a 2D-DWT lifting based architecture. This proposed multiplier eliminates the use of power consuming costly conventional multipliers. The proposed multiplier represents the signed floating point results which is the drawback of representation in Verilog implementation .A Verilog model is designed and synthesized for the proposed architecture. The synthesis results indicate that Xilinx vertix-4 FPGA implementation of the proposed technique is demonstrated which achieves Multiplier less structure, 12% reduced number of slices and 10% reduced power architecture compared with conventional one level lifting 2D-DWT architecture using 9/7 Filter

An efficient 3-dimensional discrete wavelet transform architecture for video processing application

This paper presents an optimized 3-D Discrete Wavelet Transform (3-DDWT) architecture. 1-DDWT employed for the design of 3-DDWT architecture uses reduced lifting scheme approach. Further the architecture is optimized by applying block enabling technique, scaling, and rounding of the filter coefficients. The proposed architecture uses biorthogonal (9/7) wavelet filter. The architecture is modeled using Verilog HDL, simulated using ModelSim, synthesized using Xilinx ISE and finally implemented on Virtex-5 FPGA. The proposed 3-DDWT architecture has slice register utilization of 5%, operating frequency of 396 MHz and a power consumption of 0.45 W.

A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform

This paper presents a novel unified and programmable 2-D Discrete Wavelet Transform (DWT) system architecture, which was implemented using a Field Programmable Gate Array (FPGA)-based Nios II soft-core processor working in combination with custom hardware accelerators generated through high-level synthesis. The proposed system architecture, synthesized on an Altera DE3 Stratix III FPGA board, was developed through an iterative design space exploration methodology using Altera's C2H compiler. Experimental results show that the proposed system architecture is capable of real-time video processing performance for grayscale image resolutions of up to 1920?×?1080 (1080p) when ran on the Altera DE3 board, and it outperforms the existing 2-D DWT architecture implementations known in literature by a considerable margin in terms of throughput. While the proposed 2-D DWT system architecture satisfies real-time performance constraints, it can also perform both forward and inverse DWT, support a number of popular DWT filters used for image and video compression and provide architecture programmability in terms of number of levels of decomposition as well as image width and height. Based from the design principles used to implement the proposed 2-D DWT system architecture, a system design guideline can be formulated for SOC designs which plan to incorporate dedicated 2-D DWT hardware acceleration.

Image Compression Techniques for High Resolution Satellite Imageries using Classical Lifting Scheme

The properties of Wavelet Transform can be successfully applied for analysis and processing of non stationary signals e.g., speech and image processing, data compression and communications. Due to the growing number of applications in various areas, it is necessary to explore the hardware implementation options of the Discrete Wavelet Transform (DWT). The Wavelet Series is just a sampled version of Continuous Wavelet Transform (CWT) and its computation may consume significant amount of time and resources, depending on the required resolution. The Discrete Wavelet Transform (DWT), based on sub-band coding, is a fast computation technique of Wavelet Transform, easy to implement and reduces the computational time and resources. Wavelet Transform uses multi-resolution technique by which different frequencies are analyzed with different resolutions. The study of 2-D DWT architectures reveals that there are two schemes for implementing DWT, one is based on convolution and other is based on lifting scheme. In this paper detailed study of Lifting Scheme has been carried out. Different architectures have been studied and performance parameters such as PSNR and Compression Ratio are determined. After obtaining double precision value of the image of size 256*256 imagery in BMP format, discrete wavelet transforms techniques are applied to obtain the wavelet coefficients for calculating PSNR and Compression ratio. Inverse Discrete wavelet transform are applied to get back the reconstructed image. It is found that for both satellite Rural and Urban imageries, the lifting scheme is very useful for obtaining higher quality of reconstructed images while achieving better PSNR~29 and Compression Ratios ~8.

Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines

A new discrete wavelet transform (DWT) architecture is proposed to realize a memory-efficient 2-D DWT processor. The proposed DWT processor conforms to dual-line scanning to remove the transpose buffer. In the previous single-line DWT architectures, the transpose buffer size is proportional to the row size of the image. The conventional dual-line DWT architecture is constructed by using the convolution-based filter structure and replicates registers to alternatively deal with two lines, resulting in a long delay, as well as a number of operators and registers. The proposed architecture is based on the lifting-based DWT to embed the additional registers in the middle of the DWT operation. In addition, the computation topology is optimized for the proposed dual-line DWT architecture to achieve almost the same hardware cost and critical path as the single-line DWT architecture.

Memory-Efficient and High-Performance Two-Dimensional Discrete Wavelet Transform Architecture Based on Decomposed Lifting Algorithm

The line-based method has been one of the most commonly-used methods of hardware implementation of two-dimensional (2D) discrete wavelet transform (DWT). However, data buffer is required between the row DWT processor and the column DWT processor to solve the data flow mismatch, which increases the on-chip memory size and the output latency. Since the incompatible data flow is induced from the intrinsic property of adopted lifting-based algorithm, a decomposed lifting algorithm (DLA) is presented by rearranging the data path of lifting steps to ensure that image data is processed in raster scan manner in row processor and column processor. Theoretical analysis indicates that the precision issue of DLA outperforms other lifting-based algorithms in terms of round-off noise and internal word-length. A memory-efficient and high-performance line-based architecture is proposed based on DLA without the implementation of data buffer. For an N × M image, only 2N internal memory is required for 5/3 filter and 4N of that is required for 9/7 filter to perform 2D DWT, where N and M indicate the width and height of an image. Compared with related 2D DWT architectures, the size of on-chip memory is reduced significantly under the same arithmetic cost, memory bandwidth and timing constraint. This design was implemented in SMIC 0.18µm CMOS logic fabrication with 32kbits dual-port RAM and 20K equivalent 2-input NAND gates in a 1.00mm × 1.00mm die, which can process 512 × 512 image under 100MHz.

High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform

This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D DWT with computation time as low as <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /12 can be easily achieved for an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> times <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> image with controlled increase of hardware cost. Compared with recently published 2-D DWT architectures with computation time of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /3 and 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /3, the proposed designs can also save a large amount of multipliers and/or storage elements. It can also be used to implement those 2-D DWT traditionally suitable for lifting or flipping-based designs, such as (9,7) and (6,10) DWT. The throughput rate can be improved by a factor of 4 by the proposed approach, but the hardware cost increases by a factor of around 3. Furthermore, the proposed designs have very simple control signals, regular structures and 100% hardware utilization for continuous images.

Low-Power, Low-Complexity Bit-Serial VLSI Architecture for 1D Discrete Wavelet Transform

The discrete wavelet transform (DWT) is an upcoming compression technique that has been selected for MPEG-4 and JEPG 2000, because it has no blocking effects and it efficiently determines the frequency property of the temporary signals. In this paper, we propose a low-complexity, low-power bit-serial DWT architecture, employing a two-channel lattice-based quadrature mirror filter (QMF). The filter consists of four lattices (filter length = 8), and we determine the quantization bit for the coefficients using a fixed-length peak signal-to-noise ratio analysis and propose the architecture of the bit-serial multiplier with a fixed coefficient. The canonical signed digit encoding for the coefficients is applied to minimize the number of nonzero bits, thus reducing the hardware complexity. The proposed folded one-dimensional DWT architecture processes the other resolution levels during idle periods by decimations, and it provides efficient scheduling. The proposed architecture requires only flip-flops and full adders. This architecture has been designed and verified by the Verilog HDL and synthesized using the Synopsys Design Compiler with the DongbuAnam 0.18 μm Standard Cell Library. The maximum throughput is 393 Mbps at 450 MHz with a latency of 16 clocks, and the gate count is about 5K in equivalent two-input NAND gates. The dynamic power is 7.02 mW at 1.8 V. The data scheduling using a data dependency graph, and the performance, power, and required hardware cost are discussed.

Efficient Architectures for Two-Dimensional Discrete Wavelet Transform Using Lifting Scheme

Novel architectures for 1-D and 2-D discrete wavelet transform (DWT) by using lifting schemes are presented in this paper. An embedded decimation technique is exploited to optimize the architecture for 1-D DWT, which is designed to receive an input and generate an output with the low- and high-frequency components of original data being available alternately. Based on this 1-D DWT architecture, an efficient line-based architecture for 2-D DWT is further proposed by employing parallel and pipeline techniques, which is mainly composed of two horizontal filter modules and one vertical filter module, working in parallel and pipeline fashion with 100% hardware utilization. This 2-D architecture is called fast architecture (FA) that can perform J levels of decomposition for N * N image in approximately 2N2(1 - 4(-J))/3 internal clock cycles. Moreover, another efficient generic line-based 2-D architecture is proposed by exploiting the parallelism among four subband transforms in lifting-based 2-D DWT, which can perform J levels of decomposition for N * N image in approximately N2(1 - 4(-J))/3 internal clock cycles; hence, it is called high-speed architecture. The throughput rate of the latter is increased by two times when comparing with the former 2-D architecture, but only less additional hardware cost is added. Compared with the works reported in previous literature, the proposed architectures for 2-D DWT are efficient alternatives in tradeoff among hardware cost, throughput rate, output latency and control complexity, etc.

A note on "Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet Transform"

A flipping structure for the discrete wavelet transform (DWT) was proposed by Huang et al., which aimed at shortening the critical path of the lifting-based one-dimensional (1-D) architecture and reducing the number of pipeline register used in 1-D architecture as well as the size of temporal buffer (TB) required in the line-based two-dimensional (2-D) architecture. In this paper, we explore the intrinsic relationship between the size of TB required in the line-based architecture for 2-D DWT (LBA2DDWT) and the number of registers used in a 1-D DWT module, and present a modified view on this issue that has been proposed by Huang et al. An improved method of mapping the registers used in 1-D DWT architecture to the TB required in LBA2DDWT is presented, which reduces more efficiently the size of memory required in LBA2DDWT than Huang's method. A parallel-based lifting scheme (PLS) for DWT and its VLSI architecture are presented. The proposed PLS of DWT not only reduces efficiently the critical path but also results in the equality of the forward discrete wavelet transform and inverse discrete wavelet transform implementations. Compared with Huang's method, the proposed PLS is more efficient in reducing critical path and/or the number of registers of VLSI implementation for 1-D DWT, and it can be concluded that the flipping structure of DWT is a special case of the PLS-based implementation.

A Parallel-Based Lifting Algorithm and VLSI architecture for DWT

A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Tα) to Tm + 4Tα, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.