Abstract
Design and FPGA Implementation of Two-Dimensional Discrete Wavelet Transform Architectures Using Raster-Scan Method Jassim M. Abdul-Jabbar Zahraa Talal Abed Al-Mokhtar Dept. of Computer Eng., College of Eng., University of Mosul, Mosul, Iraq drjssm@gmail.com zah_ta84@yahoo.com Abstract In this paper, an FPGA implementation of a 2-dimenional discrete wavelet transform (2-D DWT) is proposed to efficiently construct the corresponding twodimensional architecture by using the raster-scan image method for any given hardware architecture of one dimensional (1-D) wavelet transform filter. The proposed method is based on lifting scheme architecture. The resulting architectures are simple, modular and regular for computation of one or multilevel 2-D DWT. These architectures perform both low pass and high pass filter with multiplierless coefficients calculation. In addition they require a small on-chip area to download the architectures on FPGA Board (Spartan-3E). The proposed 2-D architecture consists of: external memory, Row 1-D arithmetic module, column 1-D arithmetic module and internal memory unit. The row and column 1-D arithmetic units are designed utilizing Biorthogonal filters (5/3 and 9/7). Keywords: 2-D DWT, FPGA implementation, Lifting scheme architecture, Rasterscan method. للتحويل المويجي المتقطع ذي البعدين FPGA التصميم والتنفيذ باستخدام بطريقة المسح النقطي د. جاسم محمد عبد الجبار زهراء طلال عبد علي المختار قسم هندسة الحاسوب – كلية الهندسة - جامعة الموصل – الموصل - العراق zah_ta84@yahoo.com drjssm@gmail.com الخلاصة FPGA 2- ) بإستخدام D DWT( في هذه البحث، تم اقتراح تنفيذ بنية التحويل المويجي المتقطع ذي البعدين 1- (. وتستند D( بكفاءة من خلال أسلوب صورة المسح النقطي لأي بنية مادية للتحويل المويجي ذات البعد الواحد الطريقة المقترحة على معمارية مخطط الرفع. البنية الناتجة كانت بسيطة ونموذجية ومنتظمة لحساب مستوى واحد أو 2- )، هذه البنية يمكنها تنفيذ عمليات مرشح الإمرار D DWT) عدة مستويات من التحويل المويجي المتقطع ذي البعدين الواطيء ومرشح الإمرار العالي مع إجراء الحساب للمعاملات بدون مضارب. وبالإضافة إلى ذلك فإنها تتطلب مساحة يتكون الهيكل ذي البعدين المقترح من: الذاكرة الخارجية ووحدة .(Spartan-3E) نوع FPGA صغيرة على رقاقة حساب الصف ذات البعد الواحد ووحدة حساب العمود ذات البعد الواحد بالإضافة الى وحدة الذاكرة الداخلية ذات البعد 9) ثنائية التعامد.
Highlights
The discrete wavelet transform (DWT) is developed as an effective tool for multiresolution analysis since its first presentation by Mallat [1] due to its good timefrequency characteristics
The external memory access consumes the most power in the 2-dimenional discrete wavelet transform (2-D DWT) hardware implementation
This paper has presented a high performance and low memory raster-scan architectures for the 2-D lifting scheme DWT of the 5/3 filter and 9/7 filters
Summary
The discrete wavelet transform (DWT) is developed as an effective tool for multiresolution analysis since its first presentation by Mallat [1] due to its good timefrequency characteristics. The direct implementation of DWT usually requires heavily arithmetic computations because it is essentially a two-channel filter bank (i.e. convolution method). The direct method of 2-D DWT architecture performs 1-D DWT on the every row and on every column of the image. This architecture needs a frame buffer as shown in Fig .1 which is usually an off –chip to store the intermediate data [8]. The systolic architecture may be preferred because of the smaller external memory access. This architecture requires some internal line buffer and processing elements which increase the die area and control complexity
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