Architectural Tradeoffs Research Articles

A detailed power model for field-programmable gate arrays

Power has become a critical issue for field-programmable gate array (FPGA) vendors. Understanding the power dissipation within FPGAs is the first step in developing power-efficient architectures and computer-aided design (CAD) tools for FPGAs. This article describes a detailed and flexible power model which has been integrated in the widely used Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, short-circuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of power-aware CAD tools for a variety of FPGA architectures, and is freely available for noncommercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment length, switch block topology, lookuptable size, and cluster size.

Reducing the complexity of instruction-level power models for VLIW processors

Aim of this paper is to propose a high-level power exploration framework based on an instruction-level energy model for VLIW (Very Long Instruction Word) architectures. More specifically, the present paper deals with the reduction of the complexity of the energy model of K-issue VLIW processors from exponential with respect to the number of operations within the Instruction Set O(?ISA? K ) to quadratic (O(K*?ISA?2)). The complexity of the energy model has been further simplified by automatically clustering the operations in the ISA with respect to their average energy. Globally, the proposed approach reduces the complexity of the characterization problem for a K-issue VLIW processor to quadratic (O(K*?C?2)) with respect to the number of operation clusters. In this way, a more efficient characterization of the VLIW core power consumption can been achieved, while preserving the accuracy of the power estimates. The proposed model has been further extended to provide early power figures and energy/performance trade-offs for multi-cluster VLIW architectures composed of multiple data-path units and a single instruction cache control unit. The proposed high-level power estimation methodology has been applied to the Lx 4-issue VLIW pipelined processor provided by STMicroelectronics.

Blue Gene/L advanced diagnostics environment

This paper describes the Blue Gene®/L advanced diagnostics environment (ADE) used throughout all aspects of the Blue Gene/L project, including design, logic verification, bring-up, diagnostics, and manufacturing test. The Blue Gene/L ADE consists of a lightweight multithreaded coherence-managed kernel, runtime libraries, device drivers, system programming interfaces, compilers, and host-based development tools. It provides complete and flexible access to all features of the Blue Gene/L hardware. Prior to the existence of hardware, ADE was used on Very high-speed integrated circuit Hardware Description Language (VHDL) models, not only for logic verification, but also for performance measurements, code-path analysis, and evaluation of architectural tradeoffs. During early hardware bring-up, the ability to run in a cycle-reproducible manner on both hardware and VHDL proved invaluable in fault isolation and analysis. However, ADE is also capable of supporting high-performance applications and parallel test cases, thereby permitting us to stress the hardware to the limits of its capabilities. This paper also provides insights into system-level and device-level programming of Blue Gene/L to assist developers of high-performance applications o more fully exploit the performance of the machine.

Supporting ATAM with a collaborative Web-based software architecture evaluation tool

As software companies are becoming increasingly globalised, a number of issues arise with respect to the social and environmental aspects of conducting the Architecture Tradeoff Analysis Method (ATAM), a software architecture evaluation method developed by the Software Engineering Institute. It would be fair to question the applicability of the ATAM to commercial companies. In this paper, we show that there are important issues and potential weaknesses in the ATAM from a social context. We provide suggestions for a means of overcoming these potential pitfalls through the assistance of the ubiquitous Internet. We then describe a tool dubbed ACE (ATAM Collaborative Environment), a Web-based software system that provides a common environment where stakeholders and software evaluators alike can take part in an ATAM evaluation without having to be physically collocated.

Root architectural tradeoffs for water and phosphorus acquisition.

Root architectural traits that increase topsoil foraging are advantageous for phosphorus acquisition but may incur tradeoffs for the acquisition of deep soil resources such as water. To examine this relationship, common bean genotypes contrasting for rooting depth were grown in the field and in the greenhouse with phosphorus stress, water stress and combined phosphorus and water stress. In the greenhouse, water and phosphorus availability were vertically stratified to approximate field conditions, with higher phosphorus in the upper layer and more moisture in the bottom layer. Under phosphorus stress, shallow-rooted genotypes grew best, whereas under drought stress, deep-rooted genotypes grew best. In the combined stress treatment, the best genotype in the greenhouse had a dimorphic root system that permitted vigorous rooting throughout the soil profile. In the field, shallow-rooted genotypes surpassed deep-rooted genotypes under combined stress. This may reflect the importance of early vegetative growth in terminal drought environments. Our results support the hypothesis that root architectural tradeoffs exist for multiple resource acquisition, particularly when resources are differentially localised in the soil profile. Architectural plasticity and root dimorphism achieved through complementary growth of distinct root classes may be important means to optimise acquisition of multiple soil resources.

System-level performance evaluation of reconfigurable processors

Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving increased attention. The design of such a hybrid reconfigurable processor involves a multitude of design decisions regarding the field-programmable structure as well as its system integration with the CPU core. Determining the impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.

Overview of a compiler for synthesizing MATLAB programs onto FPGAs

This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of digital signal processing (DSP) applications written in MATLAB, and automatically generates synthesizable register transfer level (RTL) models and simulation testbenches in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools onto field-programmable gate arrays (FPGAs). This paper describes how powerful directives are used to provide high-level architectural tradeoffs for the DSP designer. Experimental results are reported on a set of eight MATLAB benchmarks that are mapped onto the Xilinx Virtex II and Altera Stratix FPGAs.

Architectural trade-offs in the design of low power FIR filtering cores

There is a continuous drive for methodologies and approaches of low power design. This is mainly driven by the surge in portable computing. On the other hand, the design of low power systems for different portable applications is not a simple task. This is because of the number of constraints that influence the power consumption of a device. In addition to issues of performance and functionality, there is a need to satisfy strict test coverage constraints. The author investigate the impact of DSP architectural realisation, multiplier type, and the choice of number representation on the overall power consumption of DSP devices. Work in the literature so far has concentrated on the effect of these on a part or a section of a DSP system. Furthermore the effect of DfT circuits on the overall performance is studied. A hearing aid device is considered as an example of a system with strict power/area constraints. It is shown that the choice of multiplier architecture and number representation should be carefully considered when specific DSP architectural choices are made. The results are demonstrated with a number of specially designed DSP architectures for the implementation of FIR filtering algorithms on hearing aid devices.

Balancing hardware intensity in microprocessor pipelines

The evaluation of architectural tradeoffs is complicated by implications in the circuit domain which are typically not captured in the analysis but substantially affect the results. We propose a metric of hardware intensity (), which is useful for evaluating issues that affect both circuits and architecture. Analyzing data for actual designs, we show how to measure the introduced parameters and discuss variations between observed results and common theoretical assumptions. For a power-efficient design, we derive relations for and supply voltage V under progressively more general situations and illustrate the use of these equations in simple examples. Then we establish a relation between the architectural energy-efficiency metric and hardware intensity, and we derive expressions for evaluating the effect of modifications at the microarchitectural level on processor frequency and power, assuming the optimal tuning of the pipeline. These relations will guide the architect to achieve an energy-optimal balance between architectural complexity and hardware intensity.

6.7.3 The Raytheon Enterprise Architecture Process (REAP)

AbstractArchitecture processes have become an essential component in the construction of complex systems and in the government's evaluation of defense contractors. The Raytheon Enterprise Architecture Process (REAP) is a systems architecting process being developed by Raytheon Company to address both the needs of our customers and of Raytheon as a system integrator. This process integrates established industry and government standards including: Zachman Framework for Enterprise Architecture, C4ISR/Department of Defense Architecture Framework, Software Engineering Institute's Architecture Tradeoff Analysis Method, Unified Modeling Language, and Colored Petri Nets. The REAP initiative is being approached as a “one‐company” standardized methodology to address architecture definition, description, evolution, and assessment throughout Raytheon. The REAP facilitates higher interoperability for our customers' systems, enables the sharing of architectural best practices through common taxonomy and representation, and supports the creation of product line architecture templates to provide established architecture baselines for the design of new systems.

Application of an evaluation framework for analyzing the architecture tradeoff analysis method SM

Evaluation is a critical analytical process in all disciplines and fields and therefore also in software engineering. For developing and analyzing an evaluation method a framework of six basic components (target, evaluation criteria, yardstick, data-gathering techniques, synthesis techniques, and evaluation process) can be applied. This framework was developed based on the analysis of theoretical and methodological evaluation concepts applied in software and non-software disciplines. In particular, in this paper we present the application of the framework for analyzing the architecture tradeoff analysis method SM (ATAM SM), developed by the Software Engineering Institute (SEI). The results of the matching of the framework with the ATAM definition facilitate the identification of each evaluation component and stress some key aspects, such as the relevant role of stakeholders and the significance of attribute-based architectural styles in an ATAM evaluation.

A pipelined memory architecture for high throughput network processors

Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom ASICs. We propose a pipelined memory design that emphasizes worst-case throughput over latency, and co-explore architectural tradeoffs with the design of several important network algorithms. Through this co-exploration, we show that a programmable architecture can efficiently exploit behavior inherent to most common network algorithms to keep up with next generation network speeds.

Architectural Quality in Development Processes: A Case Study.

Software quality is expressed through various attributes, many of them are architectural. So, an architecture-focused development process, with an integrated self-evaluation, must be selected. The purpose of this research is to present the incorporation of Architectural Tradeoff Analysis Method in the Rational Unified Process which emphasizes the definition of the software architecture through its 4+1 architectural views. The improved RUP was applied to a case study: a Knowledge Management System (KMS), and the most important quality attributes for it were selected during the elaboration phase (Maintainability, Reliability and Efficiency), candidates architectures were proposed and the most suitable architecture was gotten.

A power model for routers: modeling alpha 21364 and infiniband routers

As interconnection networks proliferate to many new applications, a low-latency high-throughput fabric no longer suffices. An architectural-level power model for interconnection network routers will let researchers and designers easily factor in power when exploring architectural tradeoffs.

Data Transport and Processing in a Digital Cinema Theatre System

This paper gives an operational overview of a Digital Cinema Theatre System currently in commercial deployment. Storage, transport, encryption, and compression aspects are discussed, along with architectural tradeoffs and design choices made in the development.

5.5.3 Enabling Systems Architecture Tradeoffs Using a Systems Integration Framework

AbstractSystems integration of large information enterprises involves integrating multiple heterogeneous database systems, client‐server platforms, web application technologies, and data warehousing solutions. Lockheed Martin Management and Data Systems (M&DS) is involved in systems integration for state, local, and federal government customers. We are currently developing a Systems Integration Framework (SIF) to assist in the architecture tradeoff and selection for large information enterprises. A SIF is an environment, which will assist in the rapid prototyping and testing of architectures, and specific instantiations of the architectures using commercial tools and platforms. Over the last four years we have developed and tested architectures for client‐server applications, web applications, mobile computing applications, data warehouses, and data mining applications. Performance metrics have been collected for web application servers and client‐server applications. This paper will describe how we utilized the SIF as a rapid prototyping and tradeoff environment to support systems engineering for state government customers in domains such as law enforcement, criminal justice, and airline operations.

Modeling software architectures with goals in virtual university environment

Recently, the coupling of goal-based and user-centered approaches has resulted in a tremendous impact on the research of software engineering. However, there is no systematic way in the extant approaches to handling the effects of requirements on the structuring of software architectures. As an attempt towards the investigation of the interactions among goals, scenarios, and software architectures, we proposed, in this paper, a goal-driven architecture trade-off analysis method to analyze and construct software architectures in an incremental manner. We also identified criteria for architecture evaluation and verification and explored the possible types of realization of software architectures for goals. The proposed approach is illustrated using the problem domain of virtual university environment.

Architectural tradeoff in implementing RSA processors

An investigation of a suite of RSA processors using different exponentiation and modular arithmetic algorithms is the main theme of this paper. The execution time and the amount of hardware required of different algorithms used to implement the RSA processor are compared. The modular algorithms examined in this paper are classical modular algorithm, Barrett's modular algorithm, Hensel's odd division and Montgomery's modular algorithm. The exponentiation algorithms implemented are the left-to-right binary method, the right-to-left binary method, the Chinese remainder theorem. This work finds that the fast RSA processor is the one using the Chinese remainder theorem with right to left scan for exponentiation operations and Barrett's algorithm for modular arithmetic operations. The RSA processor using least amount of hardware is the one using the left-o-right binary method for exponentiation operations and Montgomery's algorithm for modular operations.

Optimizing the distribution of large data sets in theory and practice

AbstractMulticasting large amounts of data efficiently to all nodes of a PC clusteris an important operation. In the form of a partition cast it can be used to replicate entire software installations by cloning. Optimizing a partition cast for a given cluster of PCs reveals some interesting architectural tradeoffs, since the fastest solution does not only depend on the network speed and topology, but remains highly sensitive to other resources like the disk speed, the memory system performance and the processing power in the participating nodes. We present an analytical model that guides an implementation towards an optimal configuration for any given PC cluster. The model is validated by measurements on our cluster using Gigabit‐ and Fast‐Ethernet links. The resulting simple software tool, Dolly, can replicate an entire 2 GB Windows NT image onto 24 machines in less than 5 min. Copyright © 2002 John Wiley & Sons, Ltd.

Using NDIS intermediate drivers for extending the protocol stack. A case study

Internet protocols continuously evolve through the development of new protocols and new extensions being added to the existing protocols, as a result of the increasing demands on information transfer. Consequently, operating systems need to embed periodically the new low-level protocols and protocol extensions. Since this is not always possible, especially when proprietary operating systems are involved, the means for extending the protocol stack with kernel extensions implementing support for the new added services should be provided by the operating systems' owners. This is exactly what the authors aim to demonstrate within this paper with the IP mobility support (Mobile IP), a newly defined service, and Windows NT version 4, a proprietary operating system that does not natively implement this service. The paper addresses the architecture trade-off of a suitable protocol stack, platform configuration, and resource reusing. The case is made for an intermediate driver approach, and the paper addresses packet flow control and packet management based on reusing the Tcpip.sys provided services. The parameters affecting the architecture and processing related performance of the extended protocol stack are identified and performance data are provided. All the assertions below are based on the prototype developed by the authors.