Approximate Multipliers Research Articles

Optimized recursive approximate multipliers for edge detection and image smoothing applications

Optimized recursive approximate multipliers for edge detection and image smoothing applications

Balancing precision and efficiency: an approximate multiplier with built-in error compensation for error-resilient applications

Balancing precision and efficiency: an approximate multiplier with built-in error compensation for error-resilient applications

Design and Analysis of Optimized Approximate Multiplier Using Novel Higher-Order Compressor

The energy-efficient error-tolerant circuits have paved the way for a whole new area in low-power consumption applications with approximate computing. The approximate computing fulfills the trade-off requirement of exact computation and provides efficient performance. In this paper, a novel energy-efficient multiplier has been proposed for image processing applications. In the multiplication process, compressors are used as an important component for the reduction of partial products. Higher-order approximate 5:2 and 6:2 compressors are also designed and simulated in VIVADO using Verilog coding. The proposed higher-order compressors result in less area and low-power consumption in comparison with the existing state-of-the-art technique. These high-performance compressors are used at the multipliers’ reduction stage, resulting in an energy-efficient circuit for error-tolerant applications. All the simulations were carried out in VIVADO considering 8-bit inputs. Multiplication performance shows 37.77 % (8-bit) improvement in terms of power consumption in comparison to the conventional multiplier. The multiplication process has been done on the original, negative, and sharpened images using their masks. The proposed multiplier shows 51.36% (original image), 6.04% (negative image), and 22.44% (sharpened image) PSNR improvement in comparison to state-of-the-art work.

Two energy efficient unsigned approximate multipliers with N-4 compressors

Two energy efficient unsigned approximate multipliers with N-4 compressors

Image Multiplication Using Novel 4:1 Approximate Compressor*

Energy-efficient designs are the need of the hour for signal and image processing applications that are error-tolerant. The paper proposes a new 4:1 approximate arithmetic-based compressor developed by analyzing the probability-based tactics that have a higher degree of precision when implemented. Approximate n × n multiplier is designed using the proposed varying probability-based compressors. To validate the effectiveness of the new compressor, a 16 × 16 multiplier is designed. The n × n bit multiplier will have 2 n columns of partial products(PP), in which the least significant n−1 columns are designed using the novel approximate 4:1 compressor and most n + 1 columns are designed with the exact compressor. The results of the 16-bit multiplier are superior to the performance of the exact multiplier in terms of power, area, power-delay-product (PDP), and area-delay-product (ADP) typically by 39 % , 20 % , 44 % , and 26 % respectively for Design 1 and 14 % , 24 % , 30 % , and 21 % , respectively for Design 2. The Peak Signal to Noise Ratio(PSNR), Mean Square Error(MSE), and Structural Similarity Index Measure(SSIM) for the output images processed by new approximate multipliers are acceptable when compared with precision and energy.

A floating‐point multiplier based on angle representation method

SummaryThis article proposes a novel angle representation method for floating‐point number, which eliminates the need for DSP (Digital Signal Processor) resources and reduces the resource usage when performing floating‐point multiplication. Compared with the implementation of floating‐point multiplier using IP cores, the implementation of approximate multiplication based on lookup tables can achieve an average reduction of 58.2% in LUTs (look‐up tables) and an average increase of 20.4% in frequency for mantissa widths ranging from 3 to 12 bits. Additionally, it can also save an average of 23.2% in registers. Analysis of PDP (power‐delay product)/LUT to MRED (mean relative error distance)/PRED (probability of relative error distance) among other approximate multipliers shows that the proposed design extends the Pareto front. At last, simulation of a three‐level inverter is implemented to verify the effectiveness of the multiplier.

Area and Power Optimized VLSI Architecture of Approximate Multiplier

When it comes to error-resistant applications, approximation computing offers the ability to reduce design complexity while increasing performance in terms of size, latency, and power efficiency. This brief discusses an innovative design technique for approximating multipliers. When it comes to error-resistant applications, approximation computing offers the ability to reduce design complexity while increasing performance in terms of size, latency, and power efficiency. Within the scope of this short, a unique 4-2 approximate compressor is presented. This compressor is complimentary to existing compressors that have been developed in previous work. Additionally, A proposed multiplier is built using the compressors, a constant approximation, and error correction. The simulation results show that the designed approximation multiplier performs satisfactorily. Within the Xilinx-Vivado environment, the implementation, synthesis, and simulation are carried out and recorded using the verilog HDL programming language. Key Words: approximate multiplier, exact compressor, approximate compressor and Verilog HDL.

Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor

This paper proposes novel approximate 4:2 compressors developed using input reordering circuits and input combination probabilities. The input reordering circuit is used to reduce the hardware complexity of the proposed designs. This paper proposes two designs of approximate 4:2 compressors. This compressor is used in designing an approximate multiplier. The proposed multiplier designs utilize less energy than the already published ones due to acceptable inaccurate output/precision, which are best suitable for image processing applications. The proposed multiplier designs MUL1, MUL2, MUL3 and MUL4 saves 22.75%, 21.95%, 11.57%, and 8.95% energy than the best of the existing design 1.

Energy-Efficient Approximate Multiplier with Flexible Precision

Abstract: The method that can be utilized to increase accuracy and decrease energy use is approximate multiplication. A key component of many error-tolerant applications is multiplication. Approximate multipliers are increasingly utilized in energyefficient computing for applications tolerant of inaccuracy. Apart from multiplier performance, determining the appropriate approximate multiplier is challenging due to considerations of area and delay. Therefore, selecting the type of approximate full adder (FA) becomes a crucial decision-making factor. These adders are employed for summing partial products in multipliers. This study presents the design and evaluation of an approximate multiplier employing four distinct approximate adders. The design undergoes simulation and synthesis using Xilinx and Model Sim. Compared to previously proposed approximate multipliers, the proposed circuits demonstrate substantial reductions in area, time delay, and power consumption. According to experimental data, the area, latency, and average power consumption of the suggested adjustable approximate multiplier can be lowered by 10%, 34.96 ns, and 300 mW when contrasted to the Wallace tree multiplier.

Iterative construction of energy and quality-efficient approximate multipliers utilizing lower bit-length counterparts

Iterative construction of energy and quality-efficient approximate multipliers utilizing lower bit-length counterparts

Low-Power Approximate Unsigned and Signed Multipliers with Configurable Error Recovery

In the field of Digital Signal Processing and similar applications, Approximate circuits are being explored as a means to enhance performance and energy efficiency by sacrificing a degree of accuracy. Within these circuits, Multipliers play a crucial role and are being investigated for their potential impact on overall system optimization. In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbours for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery. The multipliers using these two error reduction strategies are referred to as Approximate Multiplier 1 (AM1) and Approximate Multiplier 2 (AM2), respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Unsigned multiplication multiplier, with the signed multiplication. The signed multiplication tends to have lower power consumption is observed. By utilizing an appropriate error recovery, the proposed approximate multipliers achieve similar processing accuracy as traditional exact multipliers, but with significant improvements in power.

High-Speed and Low-Power Recursive Rounding Based Approximate Multipliers for Error-Resilience Applications

High-Speed and Low-Power Recursive Rounding Based Approximate Multipliers for Error-Resilience Applications

Probability-based error adjustment and area-efficient approximate 4-2 compressor for approximate multiplier

Probability-based error adjustment and area-efficient approximate 4-2 compressor for approximate multiplier

Design and Analysis of Low Power Approximate Multiplier Using Novel Compressor

Design and Analysis of Low Power Approximate Multiplier Using Novel Compressor

Survey on Power and Area efficient FIR Filter Architecture in Digital Encephalography System

In the process of Electroencephalogram (EEG) acquisition, the electrical signals from the brain are contaminated by numerous noise sources and artifacts. American Clinical Neurophysiology Society recommends digital filtering of acquired EEG signals with an upper cut-off frequency of 70 Hz before display in digital encephalography systems. We propose a linear symmetrical FIR filter architecture for filtering EEG signals using approximate computation techniques. Approximate computation techniques result in lower hardware resources and lower power consumption with some compromise in quality. Software tools used for this study include MATLAB (and its FDA tool) and Xilinx ISE 14.7. The chosen target platform is the Spartan-3e starter FPGA board. We propose the architecture for an Approximate Dadda Tree Multiplier. The proposed approximate multiplier consumes 25% lesser slices and 35.18% lower dynamic power than state-of-the-art approximate multipliers. The proposed FIR filter consumes 19.77% lesser LUTs and 34.97% lower power than state-of-the-art symmetric FIR filter architectures.

Floating-Point Approximation Enabling Cost-Effective and High-Precision Digital Implementation of FitzHugh-Nagumo Neural Networks.

The study of neuron interactions and hardware implementations are crucial research directions in neuroscience, particularly in developing large-scale biological neural networks. The FitzHugh-Nagumo (FHN) model is a popular neuron model with highly biological plausibility, but its complexity makes it difficult to apply at scale. This paper presents a cost-saving and improved precision approximation algorithm for the digital implementation of the FHN model. By converting the computational data into floating-point numbers, the original multiplication calculations are replaced by adding the floating-point exponent part and fitting the mantissa part with piecewise linear. In the hardware implementation, shifters and adders are used, greatly reducing resource overhead. Implementing FHN neurons by this approximation calculations on FPGA reduces the normalized root mean square error (RMSE) to 3.5% of the state-of-the-art (SOTA) while maintaining a performance overhead ratio improvement of 1.09 times. Compared to implementations based on approximate multipliers, the proposed method achieves a 20% reduction in error at the cost of a 2.8% increase in overhead.This model gained additional biological properties compared to LIF while reducing the deployment scale by only 9%. Furthermore, the hardware implementation of nine coupled circular networks with eight nodes and directional diffusion was carried out to demonstrate the algorithm's effectiveness on neural networks. The error decreased to 60% compared to the single neuron of the SOTA. This hardware-friendly algorithm allows for the low-cost implementation of high-precision hardware simulation, providing a novel perspective for studying large-scale, biologically plausible neural networks.

Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers

Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers

Design and implementation of hybrid (radix-8 Booth and TRAM) approximate multiplier using 15-4 approximate compressors for image processing application

Design and implementation of hybrid (radix-8 Booth and TRAM) approximate multiplier using 15-4 approximate compressors for image processing application

Modeling the effects of power efficient approximate multipliers in radio astronomy correlators

Large scale Radio Telescopes for Radio Astronomy highly depend on the availability of large (digital) processing capacities for imaging. Estimates concerning power efficiency for future Radio Telescopes lead to anticipated power consumption numbers beyond feasibility. To reduce the power budget, the use of approximate multipliers within the correlator is explored. A baseband equivalent executable model of a radio synthesis telescope is constructed to assess the effects of approximate multipliers. Besides ideal multipliers with floating point accuracy, the use of accurate 8-bit multipliers and 4 different types of approximate multipliers is explored. For each of these multipliers, the energy efficiency of an individual multiplier is known and used to determine the energy efficiency improvement of a correlator when using approximate multipliers. The effects of approximation are quantified by 3 metrics (Signal-to-Noise-Ratio (SNR), Spurious-Free-Dynamic-Range (SFDR) and Root-Mean-Square (RMS) level) derived from maps constructed by the executable model based on an empty sky with only a single point source. This is considered to be the worst case scenario. For illustration purposes, a more realistic input is processed by the model as well. The metrics have been determined based on different SNR levels at the input of each antenna element. For input SNR levels up to 10 dB, all types of approximate multipliers used in this paper can be exploited to improve energy efficiency of correlators, leading to a maximum energy reduction of 19 %. For input SNR values up to 30 dB an energy improvement up to 12 % can be achieved. These percentages are based on implementations in a 40nm low power IC technology at 1 GHz.

Learning the Error Features of Approximate Multipliers for Neural Network Applications

Learning the Error Features of Approximate Multipliers for Neural Network Applications