Approximate Hardware Research Articles

Reinforcement-Learning-Based Synthesis of Custom Approximate Parallel Prefix Adders

Approximate hardware units compute a sufficiently accurate result rather than a fully accurate one using fewer transistors or equivalently logic gates than their accurate counterparts. This approach significantly saves energy while maintaining acceptable application-level quality. In this work, we focus on synthesizing custom approximate parallel prefix adders tailored to specific applications. The introduced reinforcement learning (RL) framework co-optimizes application performance and hardware complexity. An RL agent learns approximate addition strategies by exploring the entire design space and receiving feedback from hardware synthesis and application performance. Experimental results demonstrate that the synthesized adders can reduce area and power consumption by 12% and 10%, respectively, on average without compromising the error behavior of the application, or can significantly improve the application’s error metrics without degrading area and power consumption for a variety of practical applications.

MAxPy: A Framework for Bridging Approximate Computing Circuits to Its Applications

This paper presents MAxPy, a framework for bridging approximate computing (AxC) circuit design to its applications. MAxPy is an application-agnostic framework able to automatically build a cycle-accurate Python model of an approximate hardware design. This model can easily be emulated and integrated as a module in Python-based applications. We are herein proposing this framework aiming to build an AxC toolbox stimulating open research in academia to promote the integration of the existing and future open-source (i) AxC benchmarks, (ii) approximate logic synthesis tools, and (iii) P unit insights. In this paper, we demonstrate the use of MAxPy to explore the AxC design space of a Sobel filter hardware design as a case study exploiting a set of approximate adders combined with the data-driven approximate logic synthesis via probabilistic pruning. Then, we present a Pareto front for circuit area, energy, and delay reduction versus the application-level metrics: edge detection accuracy and structural similarity index (SSIM). The Pareto front results of the multiple AxC techniques herein explored show circuit area savings ranging from 40.4% to 59.1% for a 98.1% to 99.6% accuracy on edge detection application MAxPy code is open source in: github.com/MAxPy-Project

EAM: Ensemble of approximate multipliers for robust DNNs

Deep neural networks (DNNs) are one of the most prominent technologies of our time, as they achieve state-of-the-art performance in a wide range of real-world applications such as healthcare, online banking, etc. However, recent advances in deep learning have opened up a largely unexplored surface for adversarial attacks, jeopardizing the integrity of DNN systems. DNNs are vulnerable to adversarial samples that are generated by perturbing correctly classified inputs to cause DNN models to mispredict. This can potentially lead to catastrophic consequences, especially in critical and security-sensitive applications such as autonomous driving and video surveillance systems.We propose ensemble of approximate multipliers (EAM), an architectural technique that uses a combination of approximate multipliers to protect DNNs against adversarial attacks. Approximate computing is known for its effectiveness in improving the energy-efficiency of computing platforms at the cost of slight accuracy loss. Using approximation in the form of inexact multipliers is also effective for increasing robustness by injecting input-dependent noises into the outputs of DNNs. However, resiliency of DNNs against malicious attacks depends on the type of an approximate multiplier. Based on level of approximation, robustness of DNNs changes by a large margin. We exploit this variability and propose using an ensemble of different types of approximate multipliers. EAM increases robustness across a wide range of attack scenarios. In particular, we show that successful attacks against an exact DNN have poor transferability to EAM. The transferability is also poor for a black-box model where perturbed inputs are generated by a substitute model. In addition, EAM is resilient against a white-box attack scenario where an attacker has full knowledge of approximate hardware. Our ensemble technique does not require duplication of computing cores nor memory units. EAM only uses additional approximate compressors within the original multipliers. We conduct extensive experiments on a set of strong adversarial attacks. We empirically show that EAM increases robustness over the exact model with negligible impact on accuracy of benign inputs.

Slack-Aware Packet Approximation for Energy-Efficient Network-on-Chips

Network-on-Chips (NoCs) are the standard on-chip communication fabrics for connecting cores, caches, and memory controllers in multi/many-core systems. With the increase in communication load introduced by emerging parallel computing applications, on-chip communication is becoming more costly than computation in terms of energy consumption. This paper contributes to existing research on approximate communication by proposing a slack-aware packet approximation technique to reduce the energy consumed by NoCs for sustainable parallel computation. The proposed approximation technique lowers both the execution time and NoC power consumption by reducing the packet size based on slack. The slack is the number of cycles by which a packet can be delayed in the network with no effect on execution time. Thus, low-slack packets are considered critical to system performance, and prioritizing these packets during the transmission will significantly reduce execution time. The proposed technique includes a slack-aware control policy to identify low-slack packets and accelerates these packets using two packet approximation mechanisms, namely, an in-network approximation (INAP) and a network interface approximation (NIAP). INAP mechanism prioritizes low-slack packets during the arbitration phase of the router by approximating packets with high-slack. NIAP mechanism reduces the latency of the network links and switch traversals by truncating data for the low-slack packets. An approximate network interface and router are implemented to support the proposed technique with lightweight packet approximation hardware for lower power consumption and execution time. Cycle-accurate simulations using the AxBench and PARSEC benchmark suites show that the proposed approximate communication technique achieves reductions of up to 24% in execution time and 38% in energy consumption with 1.1% less accuracy loss on average compared to existing approximate communication techniques.

As-Is Approximate Computing

Although approximate computing promises better performance for applications allowing marginal errors, dearth of hardware support and lack of run-time accuracy guarantees makes it difficult to adopt. We present As-Is, an Anytime Speculative Interruptible System that takes an approximate program and executes it with time-proportional approximations. That is, an approximate version of the program output is generated early and is gradually refined over time, thus providing the run-time guarantee of eventually reaching 100% accuracy. The novelty of our As-Is architecture is in its ability to conceptually marry approximate computing and speculative computing. We show how existing innovations in speculative architectures can be repurposed for anytime, best-effort approximation, facilitating the design efforts and overheads needed for approximate hardware support. As-Is provides a platform for real-time constraints and interactive users to interrupt programs early and accept their current approximate results as is. 100% accuracy is always guaranteed if more time can be spared. Our evaluations demonstrate favorable performance-accuracy tradeoffs for a range of approximate applications.

On Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars

Applications based on deep neural networks (DNNs) have grown exponentially in the past decade. To match their increasing computational needs, several nonvolatile memory (NVM) crossbar-based accelerators have been proposed. Recently, researchers have shown that apart from improved energy efficiency and performance, such approximate hardware also possess intrinsic robustness for defense against adversarial attacks. Prior works have focused on quantifying this intrinsic robustness for vanilla networks, that is DNNs trained on unperturbed inputs. However, adversarial training of DNNs, i.e., training with adversarially perturbed images, is the benchmark technique for robustness, and sole reliance on intrinsic robustness of the hardware may not be sufficient. In this work, we explore the design of robust DNNs through the amalgamation of adversarial training and the intrinsic robustness offered by NVM crossbar-based analog hardware. First, we study the noise stability of such networks on unperturbed inputs and observe that internal activations of adversarially trained networks have lower signal-to-noise ratio (SNR), and are sensitive to noise compared to vanilla networks. As a result, they suffer significantly higher performance degradation due to the approximate computations on analog hardware; on an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> accuracy drop. Noise stability analyses clearly show the instability of adversarially trained DNNs. On the other hand, for adversarial images generated using Square Black Box attacks, ResNet-10/20 adversarially trained on CIFAR-10/100 display a robustness improvement of 20%–30% under high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\epsilon _{\mathrm{ attack}}$ </tex-math></inline-formula> (degree of input perturbation). For adversarial images generated using projected-gradient-descent (PGD) White-Box attacks, the adversarially trained DNNs present a 5%–10% gain in robust accuracy due to the underlying NVM crossbar when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\epsilon _{\mathrm{ attack}}$ </tex-math></inline-formula> is greater than the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">epsilon</i> of the adversarial training ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\epsilon _{\mathrm{ train}}$ </tex-math></inline-formula> ). Our results indicate that implementing adversarially trained networks on analog hardware requires careful calibration between hardware nonidealities and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\epsilon _{\mathrm{ train}}$ </tex-math></inline-formula> to achieve optimum robustness and performance.

Compact Modeling of Nanocluster Functionality as a Higher-Order Neuron

Disordered nanoclusters with multielectrode input–output functionality had recently been experimentally realized with energy-efficient and emergent computational capacity, and thus an interconnected network of several such nanoclusters had been proposed to realize artificial neural networks. To aid that end, here we show that nanocluster functionality can be fit to the simplest dendritic neuron model (DNM), where the only form of nonlinearity is due to multiplicative interactions. This work brings into the spotlight higher-order neural networks (known for their efficient encoding of geometric invariances) to serve as an explainable baseline model of nano-networks against which experimentalists can compare more sophisticated models (deep neural networks or physics-based models such as the lin-min network introduced here) and provides ground for designing novel approximate hardware and a statistical mechanics analysis of the learning performance of interconnected nanoclusters versus perceptrons (where neurons output a nonlinear function of the weighted sum of their inputs). A network with just ten higher-order neurons is shown to achieve a classification accuracy of more than 96% on the MNIST benchmark for handwritten digit recognition (which required 100 times more neurons in three-layer perceptrons).

Evaluation and characterization of approximate arithmetic circuits

SummaryWith the end of Dennard's scale, processor designers have been looking for new technical alternatives so that approximate computing (AC) has managed to attract the attention of researchers by offering techniques ranging from the application level to the circuit level. When applying approximate circuits into hardware design, the program user may speed up the application. At the same time, a designer may save area and power dissipation at the cost of less accuracy on the results of operations. This article discusses the compromise between controlled accuracy versus physical efficiency by evaluating a set of arithmetic circuits designs. The article also presents new mixed organization approximate designs. To evaluate the approximate design benefits, we performed a comprehensive set of experiments from tailor‐made approximate arithmetic circuits on field‐programmable gate array and application specific integrated circuits technologies. Our results reveal that our proposed mixed approximate designs have promising results on error rates, area usage, and power dissipation compared to the related work. Another interesting result is that one should care about the prototyping platform where the approximate hardware will be synthesized. Tailor‐made approximate cells may take advantage on intrinsic design details than standard cells or even general prototyping platforms.

Error-Tolerant Data Sketches Using Approximate Nanoscale Memories and Voltage Scaling

Data sketches (or summaries) are widely used to efficiently process large data sets and obtain relevant information, such as the number of distinct elements, their frequency or the similarity of several sets. Since sketches provide probabilistic estimates (hence accomplishing considerable reductions in storage and computational requirements), it seems that approximate hardware is appropriate for implementation providing an estimate rather than the exact value and enabling further improvements in metrics. In this paper, the use of voltage scaling in an approximate nanoscale FinFET-based memory for implementing sketches is studied and evaluated. To mitigate the errors introduced by the approximate memory, techniques to protect several widely used sketches when implemented in such voltage-scaled FinFET memory, are proposed. The proposed schemes preserve the sketches functionality with a negligible impact on the accuracy of their estimates and tolerate large bit error rates for sketches such as Minhash and HyperLogLog. The analysis and simulation results show that the intrinsic error tolerance of data sketches can be exploited to provide accurate estimates even when the memory suffers many errors due to the voltage scaling of the supply. Voltage scaling enables large power savings for Minhash and HyperLogLog. These initial results suggest that the use of approximate computing for data sketches is an interesting area for further research.

Optimized Image Multiplication with Approximate Counter Based Compressor

The processor is greatly hampered by the large dataset of picture or multimedia data. The logic of approximation hardware is moving in the direction of multimedia processing with a given amount of acceptable mistake. This study proposes various higher-order approximate counter-based compressor (CBC) using input shuffled 6:3 CBC. In the Wallace multiplier using a CBC is a significant factor in partial product reduction. So the design of 10-4, 11-4, 12-4, 13-4 and 14-4 CBC are proposed in this paper using an input shuffled 6:3 compressor to attain two stage multiplications. The input shuffling aims to reduce the output combination of the 6:3 compressor from 64 to 27. Design of 15-4, 10-4, 9-4, and 7-3 CBCs are performed using the proposed 6:3 compressor and the results obtained are compared with the existing models. These existing models are constructed using multiplexers and 5-3 CBC. When compared to input shuffled 5-3 the proposed 6:3 compressor shows better results in terms of area, power and delay. An approximation is performed on the 6:3 compressor to further reduce the computational energy of the system which is optimal for multimedia applications. The major contribution of this work is the development of two stage multiplier using various proposed CBC. All designs of the approximate compressor (AC) and true compressor (TC) are analysed with 8 x 8 and 16 x 16 image multiplication. The proposed multipliers also provide adequate levels of accuracy, according to the MATLAB simulations, in addition to greater hardware efficiency. As the result approximate circuits over image processing shows the stunning performance in many deep learning network in the current research which is only oriented to multimedia.

Energy Efficient Error Resilient Multiplier Using Low-power Compressors

The approximate hardware design can save huge energy at the cost of errors incurred in the design. This article proposes the approximate algorithm for low-power compressors, utilized to build approximate multiplier with low energy and acceptable error profiles. This article presents two design approaches (DA1 and DA2) for higher bit size approximate multipliers. The proposed multiplier of DA1 have no propagation of carry signal from LSB to MSB, resulted in a very high-speed design. The increment in delay, power, and energy are not exponential with increment of multiplier size ( n ) for DA1 multiplier. It can be observed that the maximum combinations lie in the threshold Error Distance of 5% of the maximum value possible for any particular multiplier of size n . The proposed 4-bit DA1 multiplier consumes only 1.3 fJ of energy, which is 87.9%, 78%, 94%, 67.5%, and 58.9% less when compared to M1, M2, LxA, MxA, accurate designs respectively. The DA2 approach is recursive method, i.e., n -bit multiplier built with n/2-bit sub-multipliers. The proposed 8-bit multiplication has 92% energy savings with Mean Relative Error Distance (MRED) of 0.3 for the DA1 approach and at least 11% to 40% of energy savings with MRED of 0.08 for the DA2 approach. The proposed multipliers are employed in the image processing algorithm of DCT, and the quality is evaluated. The standard PSNR metric is 55 dB for less approximation and 35 dB for maximum approximation.

A Quality-assured Approximate Hardware Accelerators–based on Machine Learning and Dynamic Partial Reconfiguration

Machine learning is widely used these days to extract meaningful information out of the Zettabytes of sensors data collected daily. All applications require analyzing and understanding the data to identify trends, e.g., surveillance, exhibit some error tolerance. Approximate computing has emerged as an energy-efficient design paradigm aiming to take advantage of the intrinsic error resilience in a wide set of error-tolerant applications. Thus, inexact results could reduce power consumption, delay, area, and execution time. To increase the energy-efficiency of machine learning on FPGA, we consider approximation at the hardware level, e.g., approximate multipliers. However, errors in approximate computing heavily depend on the application, the applied inputs, and user preferences. However, dynamic partial reconfiguration has been introduced, as a key differentiating capability in recent FPGAs, to significantly reduce design area, power consumption, and reconfiguration time by adaptively changing a selective part of the FPGA design without interrupting the remaining system. Thus, integrating “Dynamic Partial Reconfiguration” (DPR) with “Approximate Computing” (AC) will significantly ameliorate the efficiency of FPGA-based design approximation. In this article, we propose hardware-efficient quality-controlled approximate accelerators, which are suitable to be implemented in FPGA-based machine learning algorithms as well as any error-resilient applications. Experimental results using three case studies of image blending, audio blending, and image filtering applications demonstrate that the proposed adaptive approximate accelerator satisfies the required quality with an accuracy of 81.82%, 80.4%, and 89.4%, respectively. On average, the partial bitstream was found to be 28.6 smaller than the full bitstream .

Approximate Hardware Architecture for Interpolation Filter of Versatile Video Coding

The new Versatile Video Coding (VVC) standard was recently developed to improve compression efficiency of previous video coding standards and to support new applications. This was achieved at the cost of an increase in the computational complexity of the encoder algorithms, which leads to the need to develop hardware accelerators and to apply approximate computing techniques to achieve the performance and power dissipation required for systems that encode video. This work proposes the implementation of an approximate hardware architecture for interpolation filters defined in the VVC standard targeting real-time processing of high resolution videos. The architecture is able to process up to 2560x1600 pixels videos at 30 fps with power dissipation of 23.9 mW when operating at a frequency of 522 MHz, with an average compression efficiency degradation of only 0.41% compared to default VVC video encoder software configuration.

Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing

The approximate computing paradigm emerged as a key alternative for trading off accuracy and energy efficiency. Error-tolerant applications, such as multimedia and signal processing, can process the information with lower-than-standard accuracy at the circuit level while still fulfilling a good and acceptable service quality at the application level. The automatic detection of R-peaks in an electrocardiogram (ECG) signal is the essential step preceding ECG processing and analysis. The Haar discrete wavelet transform (HDWT) is a low-complexity pre-processing filter suitable to detect ECG R-peaks in embedded systems like wearable devices, which are incredibly energy-constrained. This work presents an approximate HDWT hardware architecture for ECG processing at very high energy efficiency. Our best-proposal employing pruning within the approximate HDWT hardware architecture requires just seven additions. The use of a truncation technique to improve energy efficiency is also investigated herein by observing the evolution of the signal-to-noise ratio and the ultimate impact in the ECG peak-detection application. This research finds that our HDWT approximate hardware architecture proposal accepts higher truncation levels than the original HDWT. In summary: Our results show about 9 times energy reduction when combining our HDWT matrix approximation proposal with the pruning and the highest acceptable level of truncation while still maintaining the R-peak detection performance accuracy of 99.68% on average.

Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy

Approximate computing trades off computation accuracy against energy efficiency. The extent of approximation tolerance, however, significantly varies with a change in input characteristics and applications. We propose a novel cross-layer approach for the synthesis of runtime accuracy-configurable hardware that minimizes energy consumption at area expense. To that end, first, we explore instantiating multiple hardware blocks in the architecture with different fixed approximation levels. These blocks can be selected dynamically and thus allow to configure the accuracy during runtime. They benefit from having fewer transistors and also synthesis relaxations in contrast to state-of-the-art gating mechanisms that only switch off a group of paths of the circuit. Our cross-layer approach combines instantiating such blocks in the architecture with area-efficient gating mechanisms that reduce toggling activity, creating a fine-grained design-time knob on energy versus area. We present a systematic methodology to explore this joint design space and find energy-area optimal solutions as a function of required accuracies, their utilization in the workload, together with hardware parameters: dynamic power savings, area of the hardware block, and leakage of the technology. Examining total energy savings for a range of circuits under different workloads and accuracy tolerances shows that our method finds Pareto-optimal solutions providing up to 32% and 60% energy savings compared to state-of-the-art accuracy-configurable gating mechanism and an exact hardware block, respectively, at 2× area cost.

A Cost-Efficient Approximate Dynamic Ranged Multiplication and Approximation-Aware Training on Convolutional Neural Networks

This paper proposes a low-cost approximate dynamic ranged multiplier and describes its use during the training process on convolutional neural networks (CNNs). It has been noted that the approximate multiplier can be used in the convolution of CNN’s forward path. However, in CNN inference on a post-training quantization with a pre-trained model, erroneous convolution output from highly approximate multipliers significantly degrades performance. On the other hand, with the CNN model based on an approximate multiplier, the approximation-aware training process can optimize its learnable parameters, producing better classification results considering the approximate hardware. We analyze the error distribution of the approximate dynamic ranged multiplication and characterize it in order to find the most suitable approximate multiplier design. Considering the effects of normalizing the biased convolution outputs, a low standard deviation of relative errors with respect to the multiplication outputs leads to a negligible accuracy drop. Based on these facts, the hardware costs of the proposed multiplier can be further reduced by adopting the partial products’ inaccurate compression, truncated input fraction, and reduced-width multiplication output. When the proposed approximate multiplier is applied to the residual convolutional neural networks for the CIFAR-100 and Tiny-ImageNet datasets, the accuracy drops of the approximation-aware training results are negligible compared with those using 32-bit floating-point CNNs.

Risk-5: Controlled Approximations for RISC-V

Approximate Computing offers enhanced energy efficiency by exploring quality relaxation on applications. Application-agnostic hardware-level techniques can provide high benefits under certain scenarios, but their integration on a general-purpose architecture presents novel control challenges. We present Risk-5, an extension of the RISC-V architecture that implements control mechanisms to orchestrate multiple coexisting approximation techniques within an architecture. In Risk-5, approximate hardware capabilities are exposed to software through identification registers, data structures, and drivers that describe the nature and configuration parameters for each approximate design. This allows the software stack to control what and how much is approximated in an application. Control options range from activating or deactivating a certain approximation (e.g., approximating ALU operations), to configuring allowable error levels (e.g., for a configurable FPU), and configuring operation parameters that may lead to probabilistic errors (e.g., setting the refresh rate for an approximate SDRAM). Approximations may be dynamically configured and combined at runtime, allowing for simplified design space exploration. Finally, supervisor- and machine-level control allows for the use of certain approximations without requiring changes to applications. In this article, we discuss the implementation of different classes of approximation techniques, detailing and evaluating how they interact with each other. Risk-5 and the selected approximations are demonstrated in the functional level in a RISC-V ISA simulator augmented with an approximate computing framework. Our experiments evaluate how six applications from different computing domains behave when subjected to a combination of approximation techniques. Our results show how Risk-5 can bridge the gap between software and hardware approximations, allowing designers to easily evaluate energy-quality tradeoffs.

Error-aware Design Procedure to Implement Energy-efficient Approximate Squaring Hardware

Background:: In recent years, there has been a high demand for executing digital signal processing and machine learning applications on energy-constrained devices. Squaring is a vital arithmetic operation used in such applications. Hence, improving the energy efficiency of squaring is crucial. Objective:: In this paper, a novel approximation method based on piecewise linear segmentation of the square function is proposed. Methods: Two-segment, four-segment and eight-segment accurate and energy-efficient 32-bit approximate designs for squaring were implemented using this method. The proposed 2-segment approximate squaring hardware showed 12.5% maximum relative error and delivered up to 55.6% energy saving when compared with state-of-the-art approximate multipliers used for squaring. Results: The proposed 4-segment hardware achieved a maximum relative error of 3.13% with up to 46.5% energy saving. Conclusion:: The proposed 8-segment design emerged as the most accurate squaring hardware with a maximum relative error of 0.78%. The comparison also revealed that the 8-segment design is the most efficient design in terms of error-area-delay-power product.

LPQ-SAM: A Low-Power Quality Scalable Approximate Multiplier

Approximate computing allows compromising accuracy to attain energy and performance efficient designs. However, the accuracy requirements of many applications change on runtime and it has been often observed that traditional approximate hardware tends to either provide unacceptable results or leads to an unnecessary computational effort. Quality scalable configurations can overcome these limitations. With the same motivation, we propose a low-power quality scalable approximate multiplier (LPQ-SAM) in this paper. This low power multiplier has various accuracy reconfigurable modes, including an accurate one and thus, it can be used for both error-resilient and exact applications. LPQ-SAM is exhaustively tested for different error metrics and it has been observed that in the approximate mode, it provides up to 19% and 55% power reduction compared to the exact Booth and Wallace multipliers, respectively. For illustration purposes, we demonstrated the effectiveness of LPQ-SAM on a real-time application, i.e., image masking.

Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges

Traditional computing systems based on the von Neumann architecture are fundamentally bottlenecked by data transfers between processors and memory. The emergence of data-intensive workloads, such as machine learning (ML), creates an urgent need to address this bottleneck by designing computing platforms that utilize the principle of colocated memory and processing units. Such an approach, known as “in-memory computing,” can potentially eliminate data movement costs by computing inside the memory array itself. Crossbars based on resistive nonvolatile memory (NVM) devices have shown immense promise in serving as the building blocks of in-memory computing systems for ML workloads. This is because their high density can lead to higher on-chip storage capacity, while they can also perform massively parallel, in situ matrix-vector multiplication (MVM) operations, thereby accelerating the main computational kernel of ML workloads. However, resistive crossbar-based analog computing is inherently approximate due to the device- and circuit-level nonidealities. Furthermore, the area and energy costs of peripheral circuits for conversions between the analog and digital domains can greatly diminish the intrinsic efficiency of crossbar-based MVM computation. We present a comprehensive overview of the emerging paradigm of computing using NVM crossbars for accelerating ML workloads. We describe the design principles of resistive crossbars, including the devices and associated circuits that constitute them. We discuss intrinsic approximations arising from the device and circuit characteristics and study their functional impact on the MVM operation. Next, we present an overview of spatial architectures that exploit the high storage density of NVM crossbars. Furthermore, we elaborate on software frameworks that effectively capture device-circuit-architecture characteristics to evaluate the performance of large-scale deep neural networks (DNNs) using resistive crossbar-based hardware. Finally, we discuss open challenges and future research directions that need to be explored in order to realize the vision of resistive crossbars as the building blocks of future computing platforms.