3D Integration Approach Research Articles

A computational approach for 3D modeling and integration of heterogeneous geo-data

This paper tackles the volumetric representation of geophysical and geotechnical data, gathered during exploration surveys of the subsoil; in particular, we focus on the modeling and analysis of underwater deposits. The creation of a 3D model as support to geological interpretation has to take into account the heterogeneity of the input data, coming from offshore acquisition campaigns. Some data are massive, but cover the domain unevenly, e.g., along dense differently spaced lines, while others are very sparse, e.g., borehole locations with soil sampling and CPTU (Piezocone Penetration Test) locations.A automatic process is presented to generate the subsurfaces and volume defining a sub-seabed deposit, starting from the identification of relevant morphological features in seismic data. In particular, simplification and refinement based on geostatistics have been applied to generate regular 2D meshes from strongly anisotropic data, in order to improve the quality of the final 3D tetrahedral mesh. Furthermore, we also use geostatistics to predict geotechnical parameters from local surveys and estimate their distribution on the whole domain: in this way the 3D model will include relevant geological features of the deposit and allow extrapolating different geotechnical information with associated uncertainty. The volume characterization and its 3D inspection will support geological analysis and planning of future engineering activities. The developed methodology has been tested on two real case studies.

A Single Side Priority Based GA Approach for 3D Printing Center Integration to Spare Part Supply Chain in Automotive Industry

A Single Side Priority Based GA Approach for 3D Printing Center Integration to Spare Part Supply Chain in Automotive Industry

Adhesive wafer bonding with ultra-thin intermediate polymer layers

Wafer bonding methods with ultra-thin intermediate bonding layers are critically important in heterogeneous 3D integration technologies for many NEMS and photonic device applications. A promising wafer bonding approach for 3D integration is adhesive bonding. So far however, adhesive bonding processes relied on relatively thick intermediate adhesive layers. In this paper, we present an adhesive wafer bonding process using an ultra-thin intermediate adhesive layer with sub-200nm thickness. We demonstrate adhesive bonding of silicon wafers with a near perfect bonding yield of >99% and achieve less than ±10% non-uniformity of the intermediate layer thickness across an entire 100 mm-diameter wafer. A bond strength of 4.8MPa was measured for our polymer adhesive, which is considerably higher than previously reported for other ultra-thin film adhesives. Additionally, the adhesive polymer used in the proposed method features excellent chemical and mechanical stability. We also report on a potential strategy for mitigating the formation of micro-voids in the polymer adhesive at the bond interface. Furthermore, the polymer adhesive can be sacrificially removed by oxygen plasma etching for both isotropic and anisotropic release etching. The characteristics of the adhesive wafer bonding process and its compatibility with CMOS wafers, makes it very attractive for heterogeneous 3D integration processes targeted at CMOS-integrated NEMS and photonic devices.

Metallic Schottky barrier source/drain nanowire transistors using low-temperature microwave annealed nickel, ytterbium, and titanium silicidation

This work presents the formation of intrinsic and dopant-segregated Schottky barrier nanowire transistors using microwave-annealed silicidation. To gain a sound understanding of applying the microwave annealing on fabricating metallic source/drain nanowire devices, three metals, nickel, ytterbium, and titanium, were utilized to form the Schottky barrier source/drain. Effects of microwave annealing on silicidation as well as segregation were intensively examined by comparing with those using rapid-thermal annealing. The drain current of ytterbium-based examples depend mildly on the applied microwave power from 200–400%, whereas the higher 300% or 400% power is most appropriate to optimize nickel-based nanowire transistors. The maximum 500% power is required on forming titanium silicidation for intrinsic or dopant-segregated nanowire devices. Relatively, temperature of 600℃ is required to form the nanowire source/drain with nickel or ytterbium, and temperature of 900℃ is needed for titanium-based devices. Experimental results show that the microwave annealing offers low-temperature processing against the rapid-thermal method to ensure favorable device characteristics, serving as a promising approach for 3D integration of CMOS technologies.

A New Approach for Reliable and Compact 3D Integration of mmW Transceivers on Silicon Using High-Impedance Surface Antennas

3D integration of heterogeneous modules including RF and millimeter-wave (mmW) functionalities is opening new challenges for packaging developers to conciliate between electrical performance, thermal behavior and mechanical reliability using cost-effective technologies. This paper deals with innovative integrated antenna solutions within the particular context of 3D heterogeneous integration on silicon interposer using a disruptive design approach. Novel integration schemes of antennas using a high-impedance surface (HIS) reflector are presented. Then, the design steps of a 60-GHz folded dipole antenna for short-range communications are detailed. Simulation and measurement results show promising performances in terms of gain and radiation efficiency. Process and fabrication issues are addressed with specific Back-End processing developments and an experimental validation is proposed.

Parts synthesis approach for 3D integration of MEMS and microsystems leading to system-on-package

This paper aims at developing Parts Synthesis Approach (PSA) for three-dimensional integration of MEMS and Microsystems leading to System-On-Package (SOP). This eliminates the interconnection related problems that arise when MEMS and its associated circuitry are packaged separately. A gas sensor array microsystem illustrates this. The novelty is that the electronics block at room temperature and the sensor at sensing temperature (250° C - 550° C) coexist in the same SOP. Targeted specifications of the SOP are low power budget per sensor and low cost. Thermal and structural modelling and analysis has been done using ANSYS software. The SOP is modular in design and construction.In PSA the six physical parts of the SOP are first designed, optimized and fabricated individually and then integrated to form the desired SOP. The substrate is an integral and active part of the SOP. Power management is done by reducing thermal mass of the hotplate, increasing thermal resistance between the hotplate and the rest of the substrate and using pulsed power operation. Designs of the cavity structure, the coverlid and the bottom support help in thermal management. This technique circumvents the difficulties of forming deep cavities in LTCC technology. Since the six different parts of the SOP are fabricated separately and then integrated together the final yield is high. Designing in parallel reduces required time and cost.