Ultralarge Scale Integration Applications Research Articles

Properties of Annealed ALD Ru from Ru(DMBD)(CO)3 and Oxygen

Ruthenium metal has a low bulk resistivity (7.1 μΩ cm), a high work function (4.7 eV), and a low solid solubility with strong adhesion to Cu, and is etchable, making Ru an attractive barrier metal or seed layer for Cu electroplating.1 For these applications, conformal deposition on the high-aspect ratio structures encountered in the back end of line (BEOL) of ultra largescale integration (ULSI) circuits is required. Atomic layer deposition (ALD), based on purge-separated dosing of precursors and self-saturating surface reactions, allows for atomic scale control and inherent high conformality. Because of these advantages, ALD processes for Ru are strongly desired. Although a number of ALD processes for Ru have been reported, currently the most widely reported Ru ALD precursor, Ru(EtCp)2, as well as other non-zero oxidation state precursors show long nucleation delays (~ 200 ALD cycles) prior to film growth. As nucleation delays can result in island growth and increased roughness and Ru films used in ULSI applications are generally only a few to tens of nanometers thick, nucleation delay is a critical growth parameter. More recent work has shown that zero oxidation state Ru precursors can significantly reduce nucleation delays for O2-based thermal ALD processes. However, the resistivities of these films are generally 18-40 µ-ohm cm, well above the bulk value. Very recently, a zero oxidation state ALD Ru process based on η4-2,3- dimethylbutadiene ruthenium tricarbonyl [Ru(DMBD)(CO)3] and O2, showed zero nucleation delay, a surface roughness of 0.6 nm RMS, and a resistivity of 14 µΩ-cm.2 Although the resistivity of films deposited using this Ru(DMBD)(CO)3 / O2 process is among the lowest values reported for ALD Ru, it still larger than the resistivity of pure ruthenium. It was speculated that residual oxygen resident in the film was the cause of the higher than bulk resistivity. In this work, we investigate the impact of annealing on the structure and electronic properties of ALD Ru. ALD Ru was deposited on either Si or Si/SiO2 substrates in a Picosun R-200 SunALE reactor at 260˚C using pure separated pulses of Ru(DMBD)(CO)3 & O2. Ru films were annealed in a reducing forming gas (4% H2 in N2) environment as well as an inert pure N2 environment at 400, 450, and 500C for various times. Resistivity is characterized via 4-pt probe, roughness via atomic force microscopy (AFM, crystallite size via x-ray diffraction (XRD), thickness and density via x-ray reflectivity (XRR), and composition via x-ray photoelectron spectroscopy (XPS). In addition, ruthenium-insulator-semiconductor (MOS) capacitors were used to extract the effective work function of the Ru. We find that post-deposition annealing reduces resistivity. For 500 C annealing in a 4% H2 / N2 ambient, resistivity was reduced from an as-deposited value of ~15 µΩ-cm to less than 10 µΩ-cm after 30 minutes and ~9 µΩ-cm after 60 mi, closely approaching the bulk value. These results indicate that ALD of Ru using Ru(DMBD)(CO)3 & O2 appears very promising for microelectronics applications. R. W. Powell, R. P. Tye, and J. Woodman Margaret, Platin. Met. Rev., 6, 138–143 (1962).D. Z. Austin et al., Chem. Mater., 29, 1107–1115 (2017).

Study on the Adhesion Strength of CVD-Cu Films with ALD-Co(W) Underlayers Made Using Amidinato Precursors

We investigated the adhesion strength of Cu films grown using chemical vapor deposition (CVD) on a Co(W) layer, which was grown using atomic layer deposition (ALD), for Cu interconnect applications in ultra-large scale integration (ULSI). Co(W) forms an effective barrier to the diffusion of Cu and forms an adhesion layer in a single barrier. Amidinato precursors were used in the deposition of Co and W, which contain neither O nor F, and yielded high-purity Co(W) films. Furthermore, the use of an amidinato Cu precursor was also found to be important in enabling Cu deposition without interfacial contamination. The W content of the Co(W) layer was optimized to 14 at% via an evaluation of the diffusion barrier properties, the electrical conductivity, and the adhesion strength with the Cu layer. A CVD-Cu/ALD-Co(W) stack was formed using amidinato precursors for the growth of both films, and was found to exhibit favorable properties compared with a conventional PVD-Cu/PVD-Ta/TaN stack. It was also favorable to a PVD-Cu/PVD-Ru/TaN stack in terms of the diffusion barrier properties and electrical conductivity, with a similar adhesion strength for Cu. For these reasons, our Co(W) films have potential applications in reliable and high-performance Cu interconnects in next-generation ULSI.

Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects

Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP) and power-delay product (PDP) of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (Id-VdandId-Vg), for subthreshold swing (SS), drain-induced barrier lowering (DIBL), and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.

Cu Electrodeposition from Methanesulfonate Electrolytes for ULSI and MEMS Applications

Methanesulfonic acid (MSA) is an alternative to sulfuric acid electrolyte for metal deposition. The electrochemical nucleation and growth of Cu on a glassy carbon electrode in methanesulfonate was compared with sulfate baths. The overpotential for Cu deposition was much smaller in the MSA bath compared to the traditional sulfuric acid bath, and Cu nucleation occurred at a higher rate in the MSA bath. The measured diffusion coefficient value for Cu deposition from the MSA bath was . UV-visible spectroscopic results confirmed that the coordination of Cu species was the same in both electrolytes. Cu electrodeposition on Ni sputtered Si substrate from the high efficiency MSA bath was photoresist-compatible with no void formation. One-dimensional Cu nanorods were also deposited through an anodized aluminum oxide template on a Ni evaporated seed layer substrate, showing potential applications as electrical interconnects in ultralarge scale integration (ULSI) and microelectromechanical systems (MEMS).

Electroless Deposited Cobalt-Tungsten-Boron Capping Barrier Metal on Damascene Copper Interconnection

The metal capping barrier deposited by the electroless cobalt tungsten boron (CoWB) alloy plating method for ultralarge scale integration applications was investigated. The CoWB film was formed directly on copper without a palladium catalyst, using dimethyl amin borane (DMAB) as a reducing agent, and it was deposited selectively on 0.25 μm wide copper interconnects separated with 0.25 μm spacing The CoWB thin films were effective barriers against copper diffusion even at CoWB thicknesses as low as 50 nm. Compared with the CoWB film, cobalt tungsten phosphorus films deposited directly on copper using DMAB as a deposition initiator was not effective as a copper diffusion barrier. The plating films contained mainly cobalt with a significant amount of tungsten (up to 20 atom %) and a small amount of boron. Additionally, we propose a newly developed alkaline metal free electroless CoWB plating solution using tetramethyl ammonium hydroxide as a pH adjuster. © 2005 The Electrochemical Society. All rights reserved.

Planarization of Copper Thin Films by Electropolishing in Phosphoric Acid for ULSI Applications

Electropolishing of thin films poses additional challenges in comparison to bulk material polishing. The existence of a resistive anode/electrolyte boundary layer is crucial for achieving polishing. A finite amount of copper is required to be anodically dissolved to create the boundary layer of the appropriate thickness for effective electropolishing of a given hillock. This is a significant consideration in the application of electropolishing for planarization of thin films where the disparity in the topography is significant in proportion to the thickness of the film. Here electropolishing is shown to effectively remove the bulk of electrodeposited copper layers used in ultralarge scale integration (ULSI) metallization schemes without application of mechanical force and to planarize local topography. Efficient polishing can be achieved under galvanostatic conditions (i.e., constant current between the wafer and a counter electrode). Anodic transient studies indicated that the mechanism of formation of the boundary layer (in mass-transport controlled regime) is determined by the diffusive transport of an acceptor species to the anode/electrolyte interface. Effects of changes in current density and rotational speed of wafer on the extent of planarization have been determined. Under optimal galvanostatic and hydrodynamic conditions, the disparity in the topography over wide trenches adjacent to dense features decreased by 60%. © 2002 The Electrochemical Society. All rights reserved.

Fabrication of Electroless NiReP Barrier Layer on SiO[sub 2] Without Sputtered Seed Layer

A new fabrication process for an electrolessly deposited NiReP barrier layer on SiO 2 is proposed for ultralarge scale integration applications. The NiReP film was formed electrolessly without sputtered seeds by utilizinga self-assembled monolayer (SAM) as an adhesion and catalyst layer. For the electroless deposition on the SiO 2 layer covered with SAM, an acid or a neutral electroless deposition bath was suitable whereas an alkaline solution damaged the SiO 2 surface. To fabricate a consistently uniform barrier film on the SAM/SiO 2 surface, a two-step process, consisting of a nucleation step performed in an acid electroless deposition bath and a barrier layer formation step carried out in an alkaline bath, is proposed. The two-step process yielded satisfactory results, and the electroless NiReP barrier layer was successfully formed on the SAM/SiO 2 surface in a high pH bath.

In Situ Rapid Thermal Oxidation and Reduction of Copper Thin Films and Their Applications in Ultralarge Scale Integration

Copper is widely accepted as a next-generation metallization material for ultralarge-scale integration (ULSI) because of its low resistivity and high electromigration resistance. It is well known that Cu oxidizes easily at low temperatures. This characteristic has impeded the application of Cu in integrated circuits. However, the high oxidation rate of Cu and high reduction rate of its oxides at low temperature can be exploited for some potential applications. This paper presents the kinetic studies of Cu film oxidation and in situ reduction of its oxide films. The Cu oxidation experiments were performed in dry and wet oxygen at temperatures from 100 to 600°C for oxidation times from 10 to 718 s. Scanning electron microscopy, Rutherford backscattering spectrometry, spectroscopic ellipsometry and reflectometry, and X-ray photoelectron spectroscopy were used for analyzing the chemical composition of the processed material and determining the oxidation/reduction kinetics of the films. The results showed that the oxide phase is CuO at higher temperature and at lower temperature (<400°C). In situ reduction of copper oxide was studied using secondary ion mass spectroscopy, indicating that the reduction of Cu oxides proceeds from the interface to the surface with a high reduction rate. The infrared reflectivity of Cu surface is over 99%. This is a problem when the Cu process is performed in a rapid thermal processing (RTP) system, since most of the radiation from the lamps is consequently reflected by the Cu surface. An improved process, called shield-enhanced RTP, results in higher lamp power efficiency and better within wafer temperature uniformity. © 2001 The Electrochemical Society. All rights reserved.

Atomic Structure of Y2O3:Eu/LaA1O3 Interfaces

There has been intense interest in preparing single crystalline yttrium oxide (Y2O3) thin films for applications in ultra-large scale integration (ULSI) gate insulators, ULSI capacitors, and, by addition of suitable dopant species, for electroluminescent devices. Y2O3 has a C-type rare-earth sesquioxide structure, closely related to the fluorite structure with a cell parameter a= 1.060 nm and space group Th (Ia3). LaAIO3 (LAO) is a rhombohedral structure with lattice parameters a = 0.378 nm, θ ≤ 90.5°. The lattice mismatch with the &lt;110&gt; direction of the YO is therefore less than 0.8%, and so we would anticipate epitaxial growth of single crystalline YO thin films on the LAO (001) substrate to be feasible. Eu activated YO thin films were deposited by laser ablation on (001) LAO substrates. TEM bright field images and electron diffraction patterns were recorded in a Philips EM-400 electron microscope operated at lOOkV. Z-contrast imaging was conducted in a VG HB603 STEM at 300kV. In this presentation, we will report the epitaxial growth of YO thin films doped with ∼ wt 4% Eu on a LaAlO3 substrate, and the atomic structure of the interface.

A Novel Pretreatment Technology for Organic Low‐Dielectric Material to Suppress Copper Diffusion and Improve Ashing Resistance

A new novel pretreatment technology for integration of organic low‐dielectric material in copper interconnects for ultralarge scale integration applications is developed. Using plasma treatment, two extremely important advantages were achieved in spin‐on organic polymer (SOP), including the reduction of copper diffusion and the improvement of ashing resistance. A copper/SOP/Si capacitor structure is used to study the electrical characteristics of SOP film after ashing treatment or postanneal. Higher barrier capability and better ashing resistance can be achieved by the SOP layer after plasma treatment. After annealing at 500°C for 60 min, secondary ion mass spectroscopy depths profile shows that the Cu atoms do not penetrate into the SOP when they are pretreated by plasma. Furthermore after the ashing step, the carbon atoms in the SOP film almost remain the same when they are pretreated by plasma. On the other hand, the concentration of carbon in as‐cured SOP is no longer seen. The reason of improving ashing resistance and better barrier capability was due to the organic polymer film rearranging to form a carbon‐containing silicon nitride film. © 2000 The Electrochemical Society. All rights reserved.

Chemical vapor deposition of copper from CuI hexafluoroacetylacetonate trimethylvinylsilane for ultralarge scale integration applications

In this article, the authors report the results of a study aimed at optimizing a manufacturable thermal copper-chemical vapor deposition process, using (tmvs) CuI (hfac) as the source, where tmvs=trimethylvinylsilane and hfac=hexafluoroacetylacetonate, and establishing associated material and process characteristics and performance. This study employed a two-stage design of experiments approach in conjunction with actual deposition runs on unpatterned silicon (Si) and titanium nitride (TiN) surfaces, as well as SEMATECH patterned TiN structures with feature sizes as small as 0.30 μm with aspect ratio 6:1. All samples were analyzed by Auger electron spectroscopy, Rutherford backscattering, four-point resistivity probe, and cross-section scanning electron microscopy. The results of these analyses showed that precursor concentration, substrate temperature, and in situ predeposition substrate surface plasma treatment play a key role in achieving good conformality and complete filling at high growth rates in aggressive via and trench structures. Based on these findings, an optimum process window was identified and employed to demonstrate complete high growth rate (∼2000 Å/min) filling of 0.3 μm, 6:1 aspect ratio, devices structures with pure copper at as-deposited resistivities of 1.8 μΩ cm.

Interconnection Formation by Doping Chemical‐Vapor‐Deposition Aluminum with Copper Simultaneously: Al‐Cu CVD

A novel chemical vapor deposition (CVD) method to form Al‐Cu wiring and via filling by simultaneous doping with Cu has been developed and its use demonstrated for advanced ultralarge scale integration applications. This new Al‐Cu CVD method was realized by using appropriate Al and Cu dimethylaluminumhydride and cyclopentadienylcoppertri‐ethylphosphine as metalorganic precursors. The deposited Al‐Cu film had a highly uniform Cu distribution and contained the phase which is indicative of a hypoeutectic Al‐Cu alloy applicable to practical interconnections. This work also showed that the electrical resistance and electromigration endurance of CVD Al can be improved by Cu incorporation with this simultaneous Cu doping method.

Copper-Based Metallization in ULSI Structures: Part II: Is Cu Ahead of Its Time as an On-Chip Interconnect Material?

The demand for manufacturing integrated circuit (IC) devices such as dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable and programmable read only memory (EEPROM) and logic devices with high circuit speed, high packing density and low power dissipation requires the downward scaling of feature sizes in ultralarge-scale integration (ULSI) structures. When chip size becomes smaller, the propagation delay time in a device is reduced. However, the importance of on-chip interconnect RC (resistance capacitance) delay to chip performance, reliability, and processing cost is increasing dramatically. When interconnect feature size decreases and clock frequencies increase, RC time delays become the major limitation in achieving high circuit speeds. The miniaturization of interconnect feature size also severely penalizes the overall performance of the interconnect, such as increasing interconnect resistance and interconnect current densities, which lead to reliability concerns due to electromigration. Lower resistance metal and lower dielectric materials are being considered to replace current Al and SiO2 interconnect materials. Innovative efforts in circuit design, process development, and the implementation of new materials can provide solutions. This issue of the MRS Bulletin focuses on the industrial viewpoint of copper interconnects. (A previous issue of the MRS Bulletin, June 1993, addressed university research approaches to copper metallization.) Articles in this issue, from six major semiconductor companies—IBM, Motorola, AT&amp;T Bell Laboratories, SEMATECH/National Semiconductor, NTT, and Fujitsu—provide a real-world viewpoint of the challenges faced when replacing aluminum with copper. The articles published in both issues also contain a comprehensive list of references (more than 300) to articles, patents, and device applications related to copper metallization for ULSI applications.

AlSiV and AlSiVPd films as alternatives for AlSiCu interconnect: microstructure and its impact on reliability

In this paper new data on highly reliable interconnect materials based on aluminium will be presented. Compared with AlSiCu alloy films, alternative alloys such as AlSiV and AlSiVPd combine excellent plasma etchability with good corrosion resistance. Addition of V to AlSi increases the electrical resistivity, but if the concentration of V does not exceed 0.2–0.3 at.%, the increase is not a problem for most practical applications in ultralarge-scale integration. AlSiV and AlSiVPd films have been subjected to electromigration stress (180°C, 2 × 10 6 A cm −2). AlSiVPd films showed suprisingly high resistance to damage. Understanding the microstructure becomes increasingly important as integrated circuit feature sizes become smaller than the average grain size of the aluminium alloy films used for interconnect. Therefore the microstructural details of the above alloys have been studied using transmission electron microscopy. Based on the results, a model has been developed which explains the action of V and Pd in the aluminium lattice. According to this model, both V and Pd are needed concurrently to obtain a high reliability Al-based interconnect. Furthermore, recent findings suggest that electromigration failure of narrow lines may be dominated by diffusion along the Al/Al-oxide interface, such that lines fail by thinning. The above model and the reliability results presented here are consistent with an interface diffusion mechanism. Finally, the (Al, Pd) precipitates observed have been characterized and identified as the decagonal “Al 75Pd 25”-type phase.

Metastable chlorine ion transport in a diverging field electron cyclotron resonance plasma

For applications in ultralarge scale integration, low pressure, high density plasmas are being developed for etching and deposition of thin films. To control critical parameters such as the flux and energy distribution of ions impacting surfaces, it is necessary to understand how these parameters are influenced by physical and electromagnetic design. In this work, we extend previous measurements of ion velocity distributions in Ar/He electron cyclotron resonance plasmas to Cl2/He plasmas. Using Doppler-shifted laser-induced fluorescence spectroscopy, we measure metastable Cl ion velocity distributions parallel and perpendicular to the magnetic field as a function of magnetic field amplitude, pressure, and microwave power. We also examine the effects of the wafer platen on the distribution functions by repeating the measurements after removing the platen. Surprisingly, little qualitative difference is seen when chlorine and argon discharges are compared; this is most likely a result of the low pressures employed (≲0.15 Pa). As in Ar, we find nearly isotropic ion velocity distributions when the source is operated as a magnetic mirror. Downstream, we consistently observe bimodal ion velocity distributions: the fast component, created in the source, appears to follow magnetic flux lines into the reactor; the slow component, created mostly where the plasma expands from the source into the reaction chamber, is more isotropic. Despite the localized input of energy by cyclotron resonance heating, the spread in ion velocities is largely determined by distributed ionization and spatial variations in the plasma potential.

Characterisation of mirror-polished Si wafers and advanced Si substrate structures using the magic mirror method

Makyoh, the magic mirror method, has proven to be one of only a few production-worthy surface characterisation tools. This technique, very simple and non-destructive, transforms latent damage, scratches, waviness and other flaws on mirror-like surfaces into visual images. It has recently been used to characterise highly finished, mirror-polished, large-diameter Si wafers for ultralarge-scale integration (ULSI) applications and III-V compound semiconductor wafers, replacing the laborious, unstable, naked-eye wafer inspection line. The authors studies have shown that the technique is also very useful for optimising various wafering processes and monitoring various process steps required to manufacture advanced substrate structures such as silicon-on-insulator, silicon-germanium alloy-on-silicon, etc for future devices. It has been successfully applied to characterise various Si wafers used in ULSI applications with the highest finish. This paper describes the recent development of the method, reviewing some of the results obtained in the evaluation of mirror-polished Si and compound semiconductor wafers and of complex substrate structures for ULSI device fabrication processes.

Synthesis of High-Quality Ultra-Thin Gate Oxides for ULSI Applications

A critical challenge in achieving ultra-large-scale-integration (ULSI) is growing ultra-thin oxides with low defect (D 0 ) and interface trap (Q it ) densities and generating a planar stress-free silicon/oxide (Si-SiO 2 ) interface. This paper describes the fabrication of a thin, multilayered, stacked SiO 2 structure with such characteristics. The dramatic improvement in the quality of these stacked oxides has been achieved through a novel synthesis of a three-step process that involves growing, depositing, and growing SiO 2 layers on silicon substrates by thermal oxidation, chemical vapor deposition, and densification/oxidation, respectively. These oxides have an ideal combination of low defect and interface trap densities. The Si-SiO 2 interface generated during the synthesis is structurally superior. Oxides of this high quality are needed — with shallow junctions and fine-line geometries — to produce scaled-down devices that can be integrated into ULSI circuits with multilevel interconnects.