Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects

Huei Chaeng Chin,Michael Loong Peng Tan,Cheng Siong Lim,Vijay K Arora,Weng Soon Wong,Kumeresan A Danapalasingam

doi:10.1155/2014/879813

Abstract

Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP) and power-delay product (PDP) of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (Id-VdandId-Vg), for subthreshold swing (SS), drain-induced barrier lowering (DIBL), and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.

Highlights

The number of transistors on a typical 1 × 1 cm chip has grown exponentially with twofold increase every 18 months keeping Moore’s Law [1] on track
This paper focuses on modeling, simulation, and benchmarking of top-gated graphene nanoribbon fieldeffect transistors (GNRFETs) against MOSFET
It is observed that there is a good agreement between GNRFET and MOSFET based on the drain current-voltage Journal of Nanomaterials

Summary

Introduction

The number of transistors on a typical 1 × 1 cm chip has grown exponentially with twofold increase every 18 months keeping Moore’s Law [1] on track. A narrow width semiconducting GNR is utilized as a channel in a top-gated transistor [13,14,15]. This pushes the limits of complementary metal-oxidesemiconductor (CMOS) type of technology beyond its limits in a GNR. This paper focuses on modeling, simulation, and benchmarking of top-gated graphene nanoribbon fieldeffect transistors (GNRFETs) against MOSFET. Logic performances of carbon and silicon-based inverter and NAND and NOR gates are assessed.

Device Modeling

Analytical Modeling of GNRFET

Device Simulation

Circuit Design

Findings

Conclusions