Signal Processing Applications Research Articles

Development of a high-performance arithmetic and logic unit for efficient digital signal processing based on reversible logic and quantum dots

Digital Signal Processing (DSP) finds a wide range of applications in various fields, including telecommunications, audio and video processing, biomedical engineering, radar systems, and image processing. Previous DSP designs faced limitations in available processing power and computational resources. Insufficient processing power could result in slower execution times, an inability to handle complex algorithms, or limited capacity to process high-speed or large-scale signals. As the demand for minimal power consumption in DSP circuits continues to grow, reversible logic and quantum-dot cellular automata (QCA) have emerged as promising technologies due to their inherent ability to reduce energy loss. Within this landscape, the arithmetic and logic unit (ALU) plays a vital role in complex circuitry, serving as a key component in digital signal processing applications. However, challenges persist, including high quantum cost and the need to limit the number of cells in the ALU design. To address these challenges, our research aims to develop an efficient ALU by integrating reversible logic and QCA technology. Our focus will be on generating essential components, such as Feynman gates, Fredkin gates, and full adder circuits, which serve as foundational building blocks for reversible logic and QCA designs. These components will be combined to construct a comprehensive ALU capable of performing 20 different operations. Our implementation efforts will be centered around QCADesigner, with a specific emphasis on digital signal processing systems that prioritize energy efficiency and optimal utilization of occupied areas.

Design Wallace Tree Multiplier Using Reversible Gates

Abstract: Multipliers are essential components in digital circuit design. They have wide spread applications in digital signal processing and communication systems. Circuit designers in VLSI design seek compact, small scale circuits with low power consumption and minimal delay. The Wallace tree multiplier is an advanced version of tree based multipliers. Numerous algorithms have been developed to create the fastest multipliers, and the Wallace tree multiplier is one such example. It utilizes reversible compressors, full adders, and half adders. The results demonstrate that the Wallace tree multiplier using reversible gates outperforms traditional multipliers in terms of power dissipation and delay, with values of 0.027W and 29.327nS re­spectively.

Construction of non-stationary biorthogonal Wavelets based on cardinal Chebyshev B-spline

In this paper, we propose a novel method for designing non-stationary biorthogonal wavelets that leverages Bezout equations to compute wavelet filter coefficients. Our approach integrates cardinal Chebyshev B-splines of varying degrees (second, third, and fourth) as bases for constructing these wavelets, providing explicit formulations for both low-pass and high-pass filters at all levels. By employing this method, we streamline the design process, making it more efficient and accessible while accommodating diverse processing requirements. The utilization of Bezout equations offers a systematic framework for deriving wavelet filter coefficients, enhancing the reproducibility and reliability of the design process. This systematic approach ensures that the resulting wavelets possess desired properties such as vanishing moments, smoothness, and optimal localization. Moreover, by incorporating cardinal Chebyshev B-splines, we can effectively capture intricate signal and image features, addressing challenges encountered in traditional wavelet design methods. Our method not only simplifies the design process but also provides a comprehensive solution by explicitly formulating filters and dual filters across all levels. This comprehensive approach ensures that the resulting wavelets meet the specific demands of applications in signal and image processing, including compression, denoising, and pattern recognition. These advancements hold significant implications for various domains, including information technology, healthcare, and engineering, where efficient and reliable processing techniques are crucial. Moving forward, it is imperative to refine algorithms, assess parameter robustness, and conduct thorough empirical validations across diverse datasets and application scenarios. This will ensure the efficacy and scalability of our proposed method and pave the way for further advancements in non-stationary wavelet design and its applications. By continuously improving and validating our approach, we can foster innovation and enhance practical outcomes in a wide range of fields.

Optimized wireless communication for 6G signal processing using memory‐augmented deep unfolding network

SummaryIn this manuscript, optimized wireless communication for 6G signals processing using memory‐augmented deep unfolding network (WC‐6G‐SP‐MADUN) is proposed. The aim of this work is to give a memory‐augmented deep unfolding network approach with a focus on belief propagation decoding of error correction codes and multiple‐input multiple‐output (MIMO) wireless systems. In contrast, compares and tabulates the performance of memory‐augmented deep unfolding methodologies with classic principled procedures, which could potentially enable 6G. Here, the wireless communication for 6G signal processing methods was used for a variety of receiver functions, including self‐interference cancelation, signal estimation and detection using memory‐augmented deep unfolding Network (MADUN), and advanced error correction by clouded leopard optimization algorithm (CLOA). Furthermore, outline the general framework of memory‐augmented deep unfolding method for any kind of signal processing application and talk about cutting edge research paths that will make it possible to build communication networks in the future. The proposed approach is implemented in MATLAB; the performance is analyzed with performance metrics such as reliability, complexity, SNR gain, convergence rate, hardware efficiency, and quantization bit width. The proposed approach attains higher SNR gain 17.96%, 24.75%, and 30.09%; lower complexity 17.92%, 23.41%, and 30.13%; and higher convergence 18.01%, 25.41%, and 31.39% when analyzed with existing techniques such as redefined wireless communication for 6G: signal processing meets deep learning and deep unfolding (RWC‐6G‐SP‐DU), lower complication deep unfolded neural network receiver for MIMO under probability data association detector (LC‐DUNN‐MIMO‐PDAD), and deep learning in physical layer communications: evolution with prospects on 5G and 6G networks (DL‐PLC‐6G), respectively.

Non-Invasive Fetal Well-Being Monitoring Approaches: A Mini Review on Fetal Signal Separation Techniques

Fetal signal separation is vital in producing an accurate interpretation of the health condition of a fetal. In the context of a non-invasive fetal monitoring approach, the signals are acquired from the abdomen of pregnant women. As a result, a mix of maternal and fetal signals is obtained. These maternal and fetal signals are vague, as both signals are interchanged during the signal acquisition stage. Since the signals are overlapped, a signal separation technique must be employed to process the fetal signal for further analysis. This paper presents published studies on applying signal processing techniques involving fetal signal separation. These papers are obtained through a strategy known as the PRISMA technique. The online databases include ACM, Emerald Publishing, IEEE Explore Digital Library, Science Direct, Scopus, and Springer, with published years spanning from 2018 until 2022. Numerous separation techniques were found, such as adaptive filtering, blind source separation (BSS), and alternative approaches. Issues on the existing methods for fetal signal separation are discussed. In addition, the limitations and drawbacks of the research work involving existing fetal signal separation are reviewed in the paper. The potential direction of future research in this field is addressed as well. Based on this mini-review, it can be concluded that noise and ambiguity can still occur in the extracted fetal signals, even when signal processing techniques are applied. In the future, deep learning would be accommodating in improving the efficiency of extracting fetal signals obtained from the non-invasive fetal well-being monitoring technique. Meanwhile, apart from fetal heart rate (fHR) detection, fetal hypoxia can also be another important focus of study for improving fetal well-being monitoring.

Investigating the existence, uniqueness, and stability of solutions in boundary value problem of fractional differential equations

This study uses fixed point theory and the Banach contraction principle to prove the existence, uniqueness, and stability of solutions to boundary value problems involving a Ψ-Caputo-type fractional differential equation. The conclusions are supported by illustrative cases, which raise the theoretical framework’s legitimacy. Fractional calculus is widely used in scientific fields, as seen by its applications in beam deflection analysis, groundwater pollution, and biomedical signal processing.

Valley Pseudospin Polarized Evanescent Coupling between Microwave Ring Resonator and Waveguide in Phononic Topological Insulators.

A coupled ring-waveguide structure is at the core of bosonic wave-based information processing systems, enabling advanced wave manipulations such as filtering, routing, and multiplexing. However, its miniaturization is challenging due to momentum conservation issues in rings with larger curvature that induce significant backscattering and radiation leakage and hampering stable operation. Here, we address it by taking an alternative approach of using topological technology in wavelength-scale and microwave ring-waveguide coupled systems built in nanoengineered phononic crystals. Our approach, which leverages pseudospin conservation in valley topological systems, eliminates phonon backscattering and achieves directional evanescent coupling. The resultant hypersonic waves in the tiny ring exhibit robust transport and resonant circulation. Furthermore, the ring-waveguide hybridization enables critical coupling, where valley-dependent ring-waveguide interference blocks the transmission. Our findings reveal the capability of topological phenomena for managing ultrahigh-frequency phonons in nano/microscale structures and pave the way for advanced phononic circuits in classical and quantum signal processing applications.

An Introduction to Bilevel Optimization: Foundations and applications in signal processing and machine learning

An Introduction to Bilevel Optimization: Foundations and applications in signal processing and machine learning

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%).

Performance Analysis of Vedic Multiplier in Hardware Implementation of Biomedical Applications

As technology advances at a rapid pace, there is an increasing need for real-time digital signal processing (DSP) applications that are efficient and swift. DSPs, or digital signal processors, are crucial components of several engineering disciplines. For processes like convolution and Fourier transforms in DSPs, rapid multiplication is essential. Multiplication is one of the basic mathematical operations used by all applications. Many different multiplier designs have been developed to boost their speed. When compared to array and booth multipliers—the products of decades of hard research—vedic multipliers are among the fastest and lowest power multipliers. The sixteen sutras, or algorithms, that the Vedic Multiplier uses are primarily logical procedures. They are the fastest and most effective because several of them have been proposed using the Urdhava Tiryakbhyam sutra. The purpose of this study is to provide an overview of the numerous biomedical applications of Vedic Multiplier in the wide field of digital signal processing, including denoising of Electrocardiogram (ECG) and Electroencephalogram ( EEG) signal. Particular attention is paid to how current Vedic Multiplier designs have been altered to increase speed and performance metrics.

Performance Analysis of Vedic Multiplier in Signal Processing Applications

The demand for quick and effective real-time digital signal processing (DSP) applications has increased due to the rapidly advancing technology. Digital signal processors, or DSPs, are essential to several engi- neering specialties. In DSPs, quick multiplication is crucial for operations like Fourier transformations and convolution. One of the fundamental arithmetic processes required by all applications is multiplication. To increase their speed, numerous multiplier designs have been created. Vedic multipliers are among the quick- est and lowest power multipliers compared to array and booth multipliers which are the result of decades of intensive research. The Vedic Multiplier works with sixteen sutras, or algorithms, most of which are for logical processes. Since several of them have been proposed utilizing the Urdhava Tiryakbhyam sutra, they are the fastest and most efficient. This paper's goal is to summarise the many uses of Vedic Multiplier in the broad field of digital signal processing such as image processing, with a focus on the various ways that Vedic Multiplier designs that are now in use have been modified to improve speed and performance metrics.

Digital IIR filters: Effective in edge preservation?

Infinite Impulse Response (IIR) filtering stands as a fundamental technique in various signal processing applications. Despite its widespread use, the scientific community widely acknowledges the suboptimal nature of IIR filters in preserving edges or abrupt transitions in piecewise signals. In situations where meticulous preservation of abrupt signal transitions is crucial, signal processing practitioners often explore alternative methodologies tailored to specific application demands. Consequently, the effectiveness of digital IIR filters in preserving signal edges while filtering out undesirable noise components continues to be a topic of active debate.In response to this limitation (or answering the question posed by the above title), the paper demonstrates that the suboptimal nature of IIR filters in preserving edges arises from the conventional methodology used to compute the output of zero-phase IIR filters. The standard method of output computation equates to solving an unconstrained optimization problem with an ℓ2-norm penalty term. Following this analysis, the paper introduces a refined approach to compute the output of digital IIR filters, aiming to overcome the challenge of preserving abrupt signal transitions. This innovative proposal replaces the ℓ2-norm with an ℓ1-norm, resulting in the development of an IIR filter that dynamically adjusts its coefficients based on the input signal. As a result, this novel approach to output computation effectively preserves essential signal features while simultaneously reducing noise, highlighting the efficacy of digital IIR filters in edge preservation. Therefore, the answer to the aforementioned question greatly depends on the chosen method for computing the output. By employing the suggested approach, the answer is unequivocally yes.

Signal Processing Techniques of Lamb Waves for Structural Health Monitoring System - A Review

The structural health monitoring (SHM) system using Lamb wave approach has drawn a lot of interest because of its outstanding performance in terms of accuracy and adaptability. The implemented signal processing techniques in the diagnostic analysis are specifically reviewed in this work. The primary factors of the wide range of applied signal processing techniques are due to the multimode and dispersive behaviour of the Lamb waves. Several Lamb modes occur simultaneously, and because they have different dispersive characteristics, they can produce complicated superimposed signals. To effectively diagnose the observed signals, several mode separations approaches have been proposed. Generally, time-frequency representation is applied for signal processing techniques. The findings demonstrated that the proposed procedures were successful in decomposing the superimposed mode into individual modes for further analysis. All these works have shown how SHM systems based on Lamb waves have evolved over time to control and monitor the condition of the structure.

FPGA Implementation of Power-efficient Multipliers for Digital Signal Processing Applications

Background:: Higher power consumption raises chip temperature because it draws more current from the power source, which directly affects how long the batteries survive in portable devices. High temperature affects the dependability and functionality of a circuit, requiring more complex packaging and cooling strategies. One of the most significant challenges in VLSI design is power consumption. The power consumption of the circuit rises with both transistor density and chip complexity. In addition, one of the essential building blocks of hardware in the majority of VLSI applications and digital signal processing systems is the multiplier. Aims and objective:: This study aimed to design and compare array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. Methodology:: In this paper, authors designed array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. For comparison, the VIVADO tool was used to simulate and synthesize multiplier outputs. Results:: Wallace tree multipliers resulted in 31.153mW, 13.220mW, 4.099mW, and 0.988 mW of power dissipation for 16-bit, 8-bit, 4-bit, and 2-bit, respectively. The best multiplier was designed using different logic like AOI, OAI, NAND-NAND, and NOR-NOR and was compared based on power dissipation. It was observed that 2.256mW power dissipation was observed for NOR-NOR logic, which was minimal among other logics. Conclusion:: The 4-bit Wallace multiplier using NOR-NOR logic was used for FPGA implementation, which can be used in digital signal processing applications.

Imperfect phononic crystals work too: The effect of translational and mid-plane symmetry breaking on hypersound propagation

Translationally symmetric nanostructures, termed phononic crystals (PnCs), offer control over the propagation of acoustic phonons in the gigahertz (GHz) range for signal-processing applications and thermal management at sub-Kelvin temperatures. In this work, we utilize Brillouin light scattering to investigate the impact of symmetry breaking on GHz phonon propagation in PnCs made of holey silicon nanomembranes. We show that the lattice of thimble-like holes leads to broken mid-plane symmetry and, hence, to anticrossing acoustic band gaps. With the rising level of uncorrelated translational disorder, the phononic effects are gradually suppressed, starting at higher frequencies. Strikingly, the low-frequency partial Bragg bandgap remains robust up to the highest level of disorder.

Inkjet printed IGZO memristors with volatile and non-volatile switching

Solution-based memristors deposited by inkjet printing technique have a strong technological potential based on their scalability, low cost, environmentally friendlier processing by being an efficient technique with minimal material waste. Indium-gallium-zinc oxide (IGZO), an oxide semiconductor material, shows promising resistive switching properties. In this work, a printed Ag/IGZO/ITO memristor has been fabricated. The IGZO thickness influences both memory window and switching voltage of the devices. The devices show both volatile counter8wise (c8w) and non-volatile 8wise (8w) switching at low operating voltage. The 8w switching has a SET and RESET voltage lower than 2 V and − 5 V, respectively, a retention up to 105 s and a memory window up to 100, whereas the c8w switching shows volatile characteristics with a low threshold voltage (Vth < − 0.65 V) and a characteristic time (τ) of 0.75 ± 0.12 ms when a single pulse of − 0.65 V with width of 0.1 ms is applied. The characteristic time alters depending on the number of pulses. These volatile characteristics allowed them to be tested on different 4-bit pulse sequences, as an initial proof of concept for temporal signal processing applications.

High-Q quasi-bound states in the continuum in C2-symmetric metasurface with enhanced second harmonic generation in two-dimensional materials

Quasi-bound states in the continuum (Quasi-BIC) possess a high quality-factor (Q-factor) that can amplify local electromagnetic fields and nonlinear effects such as second harmonic generation (SHG). In this paper, we propose a silicon metasurface with C2 symmetry. By tuning the structural parameters without breaking the C2 symmetry, three symmetric protected BICs (SP-BICs) are transformed into sharp quasi-BICs dominated by different modes in the nearinfrared spectrum. The quasi-BICs exhibit Q-factors as high as 10370 in C2 symmetric metasurface. Numerical simulations reveal that the toroidal dipole (TD) and magnetic dipole (MD) enhance intercellular coupling and local electromagnetic fields, laying the foundation for generating metasurface with high Q-factor. Furthermore, the longitudinal radiative component of electric quadrupole (EQ) outside the facet promotes enhanced light interaction with the 2D material. Leveraging the robust local electromagnetic fields and radiation characteristics of these quasi-BICs, we have achieved substantial SHG enhancement across multiple wavelengths under continuous wave (CW) operation. The SHG from 2D GaSe flake reaches 14189-fold enhancement. Our results not only offer insights into designing metasurface structures with high Q-factors but also explore the methods of enhancing the interaction between metasurface and 2D materials. The proposed nanostructure has numerous potential applications in nonlinear optics, optoelectronics and signal processing.

Analysis of Eeg Data Using Different Techniques of Digital Signal Processing

This paper explores the application of digital signal processing (DSP) techniques in the examination of electroencephalogram (EEG) data. DSP encompasses a collection of mathematical algorithms designed to employ signals, such as EEG recordings, and finds application in diverse domains, including sleep medicine, neuroscience, and biomedical engineering. Employing DSP methods for EEG data analysis enables the extraction of pertinent insights from EEG signals, the identification of event-related patterns, and the enhancement of diagnostic and therapeutic practices across various disciplines. This article provides an overview of prevalent DSP methodologies employed in EEG signal processing, encompassing filtering, power spectral analysis, wavelet analysis, independent component analysis, and artifact removal.

Design and Analysis of 16-bit pipelined subranging SAR ADC and TDC

Analog to digital converters plays an important role in medical and signal processing applications. This paper proposes a 16-bit time based analog to digital converter (ADC) architecture by combining SAR Analog to Digital Converter and Vernier Time to Digital Converter. SAR analog to digital Converter is best suited for low power, high resolution and moderate applications. Vernier Time to Digital Converter with a high resolution to increase the conversion gain of VTC. The SAR ADC and Vernier TDC are pipelined to increase the conversion speed and reduce the area, power dissipation significantly smaller. A 16-bit combined pipelining SAR ADC and Vernier TDC was designed and simulated in Tanner EDA Tool.

Time-varying graph learning from smooth and stationary graph signals with hidden nodes

Learning graph structure from observed signals over graph is a crucial task in many graph signal processing (GSP) applications. Existing approaches focus on inferring static graph, typically assuming that all nodes are available. However, these approaches ignore the situation where only a subset of nodes are available from spatiotemporal measurements, and the remaining nodes are never observed due to application-specific constraints, resulting in time-varying graph estimation accuracy declines dramatically. To handle this problem, we propose a framework that consider the presence of hidden nodes to identify time-varying graph. Specifically, we assume that the graph signals are smooth and stationary on the graphs and only a small number of edges are allowed to change between two consecutive graphs. With these assumptions, we present a challenging time-varying graph inference problem, which models the influence of hidden nodes in terms of estimating the graph-shift operator matrices that have a form of graph Laplacian. Moreover, we emphasize similar edge pattern (column-sparsity) between different graphs. Finally, our method is evaluated on both synthetic and real-world data. The experimental results demonstrate the advantage of our method when compared to existing benchmarking methods.