Digital Signal Processing Applications Research Articles

An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm

ABSTRACT The digital filters play a significant role in the field of digital signal processing (DSP). The finite impulse response (FIR) filter is an attractive choice because of the ease of design and good stability. The digital filters have a wide variety of applications such as signal processing, control systems, telecommunication, etc. They are better than the analogue filters due to their performance. In recent times, software radios have achieved attention owing to requirements for integrated and reconfigurable communication systems. Hence, reconfigurations have emerged as a significant problem in the designs of FIRs. To match the frequencies of DSP applications, higher-order FIRs are required. If length of filters rises, addition and multiplication operations also increase. This paper proposes an efficient hardware design of RFIR that employs modified bacterial foraging optimizations (MBFOs) and common sub-expression eliminations (CSEs) in its executions. MBFOs output restricted counts of filter coefficients with sums of signed-power-of-two (SPT) terms while maintaining the quality of filtered responses. On obtaining coefficients, eliminations are executed by CSEs where hardware complexities are determined in terms of adders. Model sim software validated RFIRs using the Verilog code. The proposed design of RFIRs was compared with existing designs in terms of power usages, frequencies and areas.

Enhancing Computer Digital Signal Processing through the Utilization of RNN Sequence Algorithms

With the increase in computing power and the availability of large amounts of data, deep learning techniques, especially convolutional neural networks (CNNS) and recurrent neural networks (RNNS), have become important tools for processing complex signals. These methods show excellent performance in speech recognition, image processing, natural language processing and so on. In this paper, we explore the application of recurrent neural network (RNN) sequence algorithms in the field of computer digital signal processing, highlighting current artificial intelligence techniques and their capabilities in solving complex signal processing problems. First, the paper reviews the basic principles and development of deep learning and RNN sequence algorithms, highlighting the advances these advanced technologies have made in simulating the way the human brain processes information. The practical application and effect of RNN sequence algorithm in computer digital signal processing are demonstrated through experimental data. By comparing with traditional algorithms, we demonstrate the efficiency and accuracy of RNN in processing complex signals, such as speech recognition in noisy environments and real-time video data processing. The experimental data not only demonstrate the effectiveness of RNNS in this field, but also highlight the unique advantages of deep learning methods when dealing with large and high-dimensional data. Through these empirical studies, this paper aims to provide researchers and engineers with an in-depth understanding of the potential of RNNS in digital signal processing applications, and looks forward to the future development direction of artificial intelligence technology in this field.

Design of 4-bit absolute value detector with low energy

The article highlights the latest developments in the design of low-power 4-bit Absolute Value Detector (AVD) circuits that are utilized in digital signal processing (DSP) applications. DSP applications like audio and video processing, biological signal processing, and digital communication systems rely heavily on the AVD circuit, which determines the absolute value of an input signal. The article introduces a low-energy 4-bit AVD circuit based on pass transistors that incorporates advanced optimization techniques like adiabatic logic, approximation techniques, and layout optimization. This optimized AVD circuit achieves remarkable results in terms of power consumption and energy efficiency. With a power consumption of just 0.6 nW and an energy efficiency of 0.6 pJ per cycle, the circuit maintains precision and rapid response time. These advancements in AVD circuit design can be highly beneficial for portable and battery-powered devices such as earplugs, implants, and cell phones, as well as electronic components like Static Random Access Memory (SRAM) and motherboards. Overall, the proposed low-energy 4-bit AVD circuit is a significant development in the DSP field, enabling more efficient and effective processing of digital signals.

Design and implementation of hybrid logic based MAC unit using 45 nm technology

Digital signal processing algorithms, at times, necessitate the execution of a substantial quantity of mathematical operations to speed up and iterate upon a particular data set. Numerous digital signal processing (DSP) applications impose limitations on delay, necessitating the accomplishment of DSP operations within a predetermined timeframe, hence rendering deferred processing not feasible. Therefore, digital signal processing (DSP) necessitates a multiplier and accumulator (MAC) unit that exhibits fast speed, high throughput, and low power consumption. This research aims to develop and execute a low-power MAC unit utilising a hybrid logic technique to achieve power efficiency. A MAC unit has been purposefully designed with suitable geometries to provide optimised power, area, and delay characteristics. Estimating the delay in the MAC unit depends upon data flow analysis between the MAC blocks, explicitly focusing on low-power concerns. The developed hybrid adder cell possesses several advantageous characteristics, including a high operational speed, low power consumption, minimal transistor count. The MAC architecture uses a 45 nm CMOS technology with the Mentor Graphics tool. This research additionally examines different designs of multipliers and adders that are well-suited for the execution of high throughput signal processing while simultaneously achieving low power consumption. The registers in the MAC have been implemented in GDI logic using Multi Bit Flip flops technique to achieve low power operation. The entire MAC circuitry operates on a voltage supply of 1 V. The hybrid logic MAC architecture that has been developed demonstrates a significant decrease in area consumption, amounting to a reduction of 68 % when compared to the typical CMOS logic design. Hybrid logic demonstrates a power consumption that is 92 % better compared to CMOS logic.

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW.

Phased array antenna controlled by FPGA-ARM Cortex-M Processor

This paper discusses the architecture of an adaptive transmitting antenna array that allows highly flexible beamsteering. Antenna arrays are used in many digital signal processing applications due to their ability to locate signal sources. The Direction of Arrival (DOA) estimation is a key task of array signal processing, with the Taguchi method and Multiple Signal Classification (MUSIC). Although various algorithms have been developed for DOA estimation, their high complexity prevents their use in real-time applications. In this paper, we design and develop an implementation using Field Programmable Gate Array (FPGA Artix-7), which is the most widely used ARM processor in embedded systems. The antenna array is digitally controlled with the phases synthesized by the Taguchi method.

4-bit absolute value detection for digital signal processing applications

In recent years, as the rapid advancement of the electronic industry and the higher requirements for instruments and circuits, the absolute value circuit has found an increasingly wide utilization in digital signal processing. An absolute value detector is one of the most widely used algorithms used for detecting spikes. Based on traditional designs of absolute value circuits, many optimized designs with better performance have been proposed. Based on previous analysis and research, absolute value circuits can be optimized into different sructures to meet different application requirements. This paper introduces three different absolute value circuits for different uses in digital signal processing by comparing the optimized parts to traditional absolute value circuits and introducing how the optimization can meet the needs of different applications. These optimized absolute value circuit meet the requirements of higher precision and more stable temperature in biological signal processing field, more convenient to apply in the analog-to-digital conversion in ADC field and minimization the latency energy in chip signal processing field. Absolute value circuits can be optimized in different ways to be applied in more fields in the future.

Energy Efficient Compressor Cell for Low Power Computing

As the use of multimedia devices is rising, power management is becoming a major challenge. Various types of compressors have been designed in this study. Compressor circuits are designed using several circuits of XOR-XNOR gates and multiplexers. XOR-XNOR gate combinations and multiplexer circuits have been used to construct the suggested compressor design. The performance of the proposed compressor circuits using these low-power XOR-XNOR gates and multiplexer blocks has been found to be economical in terms of space and power. This study proposes low-power and high-speed 3-2, 4-2, and 5-2 compressors for digital signal processing applications. A new compressor has also been proposed that is faster and uses less energy than the traditional compressor. The full adder circuit, constructed using various combinations of XOR-XNOR gates, has been used to develop the proposed compressor. The proposed 3-2 compressor shows average power dissipation 571.7 nW and average delay 2.41 nS, 4-2 compressor shows average power dissipation 1235 nW and average delay 2.7 nS while 5-2 compressor shows average power dissipation 2973.50 nW and average delay 3.75 nS.

A Design and Investigation Inexact Compressor Based on Low Power Multiplier

To achieve low power consumption and high performance, an approximate multiplier is a commonly used operation. A new approximate computation method has been used for Error Tolerant Image Processing applications. This operation is popular in error tolerance applications. Inexact computing is applied to error-tolerant digital signal processing applications where error can be tolerated. Multiplier is the basic unit of arithmetic logic unit of any computer computational unit. In this paper, a new approximate compressor computation method is proposed for error-tolerant image processing applications. An approximate compressor has been designed for better output power with an improved figure of merit. A comparison of the proposed compressor with the previous 4:2 compressor design has been investigated and a reduction in area, delay and power consumption has been achieved. A similar algorithm has been applied to 8-bit multiplier applications which have considerable error performance. With the newly designed multiplier using a compressor, the simulation results compared the best power utilization. The results of designing the multiplier indicate that the proposed design of a multiplier using an approximate compressor achieves a reduction in power by 129[Formula: see text]mw.

50 GHz Operation of RSFQ Arithmetic Logic Unit Designed Using the Advanced Design Flow and the Dual RSFQ/ERSFQ Cell Library

Arithmetic Logic Unit (ALU) is an integral part of digital signal processing applications and computing systems. We used ALU, based on Kogge-Stone adder, as a reference circuit to experimentally validate the advanced design flow and the dual RSFQ/ERSFQ standard cell library. Using the advanced design flow, the ALU sub-blocks were optimized across multiple process corners using Monte-Carlo simulations incorporating statistical variations in the process parameters. The correct operation of ALU was verified in the digital HDL simulation using static timing analysis pre-fabrication. We designed the RSFQ 1-bit and 4-bit ALU using the standard cell library approach for MIT-LL 100 µA/µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fab node. For the ERSFQ 1-bit ALU, the bias current overhead for the feeding JTLs was designed to be 100% of the ERSFQ DUT bias current. The RSFQ 1-bit ALU, designed for low frequency functional testing, demonstrated greater than ±15% bias margins. We demonstrated successful operation of the RSFQ 4-bit ALU with greater than ±6% bias margins at 20 GHz, greater than ±5% bias margins at 40 GHz, and greater than ±4% bias margins at 50 GHz clock frequency with BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . The ERSFQ 1-bit ALU worked up to 30.72 GHz clock frequency with BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . In addition, we analyzed the model-to-hardware correlation for the INIT sub-block of the ALU. The simulations accounted for critical current density ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> ) and sheet resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R_s</i> ) process parameters. We noted the discrepancy in simulated and measured margins and studied that a 15% higher <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> in simulations results in better model-to-hardware correlation for the INIT sub-block.

Reversible Logic based Cryptography Design Algorithm using Random Keys

Reversible computations, besides quantum computing, have various applications in digital signal processing, nanotechnology and bioinformatics. They are particularly useful in designing low-power devices and improving computational efficiency. Cryptography is vital for protecting sensitive information in fields such as bioinformatics and digital signal processing where private data is frequently exchanged. However, cryptographic algorithms can consume significant power and require large areas, particularly when implemented in hardware. Reversible logic gates offer a potential solution by being more power-efficient and potentially reducing implementation area. Using random numbers as keys for both encryption and decryption in a reversible logic gate-based cryptographic algorithm can enhance security. LSB watermarking is a technique to embed additional metadata into digital media, improving data security. To evaluate the performance of the Field Programmable Gate Array for the Reversible Logic Gate Cryptography Design architecture, comparing it to the other state-of-the-art approach is necessary.

Hybrid Protection of Digital FIR Filters

A digital finite impulse response (FIR) filter is a ubiquitous block in digital signal processing applications and its behavior is determined by its coefficients. To protect filter coefficients from an adversary, efficient obfuscation techniques have been proposed, either by hiding them behind decoys or replacing them by key bits. In this article, we initially introduce a query attack that can discover the secret key of such obfuscated FIR filters, which could not be broken by the existing prominent attacks. Then, we propose a first of its kind hybrid technique, including both hardware obfuscation and logic locking using a point function for the protection of parallel direct and transposed forms of digital FIR filters. Experimental results show that the hybrid protection technique can lead to FIR filters with higher security while maintaining the hardware complexity competitive or superior to those locked by prominent logic locking methods. It is also shown that the protected multiplier blocks and FIR filters are resilient to existing attacks. The results on different forms and realizations of FIR filters show that the parallel direct form FIR filter has a promising potential for a secure design.

Designing of 2d-IIR Filter Using a Fused ESMA-Pelican Optimization Algorithm (FEPOA)

Many Digital Signal Processing (DSP) applications and electronic gadgets today require digital filtering. Different optimization algorithms have been used to obtain fast and improved results. Several researchers have used Enhanced Slime Mould Algorithm for designing the 2D IIR filter. However, it is observed that the Enhanced Slime Mould Algorithm did not achieve a better solution structure and had a slower convergence rate. In order to overcome the issue a fused ESMA-pelican Optimization Algorithm (FEPOA) is utilized for designing the 2D IIR filter which incorporates the pelican Optimization Algorithm with the Enhanced slime Mould Algorithm (ESMA). At first, the Chaotic Approach is utilized to initialize the population which provides the high-quality population with excellent population diversity, after that the position of population members is to identify and correct the individual in the boundary search region. After that, by the pelican Tactical Approach is to examine the search space and exploration power of the FEPOA, then the Fitness is calculated randomly, and the best solution will be upgraded and then moved towards the iterations. It repeats the FEPOA phases until the execution completes. Then the best solution gives the optimal solution, which enhances the speed of convergence, convergence accuracy and the performances of FEPOA. The FEPOA is then implemented in the IIR filter to improve the overall filter design. The results provided by FEPOA accomplish the necessary fitness and best solution for 200 iterations, and the amplitude response will achieve the maximum value for =2,4,8 as well as the execution time of 3.0158s, which is much quicker than the other Genetic Algorithms often used for 2D IIR filters.

Implementation of Hardware and Energy Efficient Approximate Multiplier Architectures Using 4-2 Compressor for Images

Abstract: Approximate computing is tentatively applied in some digital signal processing applications which have an inherent tolerance for erroneous computing results. The approximate arithmetic blocks are utilized in them to improve the electrical performance of these circuits. Multiplier is one of the fundamental units in computer arithmetic blocks. Moreover, the 4-2 compressors are widely employed in the parallel multipliers to accelerate the compression process of partial products. In this brief, three novel approximate 4-2 compressors are proposed and utilized in 8-bit multipliers. Meanwhile, an error-correcting module (ECM) is presented to promote the error performance of approximate multiplier with the proposed 4-2 compressors. In this brief, the number of the approximate 4-2 compressor’s outputs is innovatively reduced to one, which brings further improvements in the energy-efficiency. This Design is implemented using Verilog HDL and simulated by Modelsim 6.4 c and synthesized by Xilinx tool.

Design and Analysis of Multiplexer based Approximate Adder for Low Power Applications

Low power consumption is crucial for error-acceptable multimedia devices, with picture compression approaches leveraging various digital processing architectures and algorithms. Humans can assemble useful information from partially inaccurate outputs in many multimedia applications. As a result, producing exact outputs is not required. The demand for an exact outcome is fading because new innovative systems are forgiving of faults. In the domain where error-tolerance is accepted, approximate computing is a new paradigm that relaxes the requirement for an accurate modeling while offering power, time, and delay benefits. Adders are an essential arithmetic module for regulating power and memory usage in digital systems. The recent implementation and use of approximate adders have been supported by trade-off characteristics such as delay, lower power consumption. This study examines the delay and power consumption of conventional and approximate adders. Also, a simple, fast, and power-efficient multiplexer-based approximate adder is proposed, and its performance outperforms the adders compared with existing adders. The proposed adder can be utilized in error-tolerant and various digital signal processing applications where exact results are not required. The proposed and existing adders are designed using EDA software for the performance calculations. With a delay of 81 pS, the proposed adder circuit reduces power consumption compared to the exact one. The experiment shows that the designed approximate adder can be used to implement circuits for image processing systems because it has a smaller delay and uses less energy.

Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams

Multiplier circuit covers a more extensive area of embedded system application in digital signal processing, cryptography, and multimedia. Nonstandard implementations and custom optimization are being done to reduce the size of multipliers. The circuit became prone to a buggy, and hence the demand for verification increased. Formal verification methods, such as satisfiability (SAT), symbolic computer algebra (SCA), and binary decision diagrams (BDDs) have made massive progress over the last few decades. However, these methods are insufficient to verify the optimized multipliers. SAT-based equivalence checking is computationally expensive. SCA-based backward rewriting is limited to algebraic-friendly multipliers. The complexity of BDDs is exponential with the input size. Although, by allowing an additional variable method, the size of the BDD is limited to 4th degree polynomial of the number of the inputs, this method is not explored to verify optimized multipliers. This article focus on verifying integer multipliers with diverse architectures. We propose an algorithm for the direct construction of BDDs without traversing circuits and generate BDDs up to 1024 bits. We utilize the additional variable method and constructing BDDs using high-to-low variable ordering. We reduce the complexity of BDD size to a 3rd degree polynomial. We generate BDDs and verify the multipliers with various architectures up to 64 bits. We propose a method to verify optimized multipliers by checking equivalence and verifying up to 32-bits optimized multipliers. We do the error tolerance analysis of our approach by inserting bugs in a circuit at various locations.

Comparison and design of energy-efficient approximate multiplier schemes for image processing by CNTFET

ABSTRACT Approximate computing is an emerging paradigm that can tolerate some loss of accuracy to improve the energy consumption and design complexity. Multiplication is one of the important computational components in various digital signal processing (DSP) applications. Improvement of multipliers, as the building blocks of an approximate computing systems, has received significant attention. Compressors are key elements in an approximate multiplier to have an optimal design with high performance. This paper proposes an approximate/exact 4–2 compressor and an exact 5–2 compressor in carbon nanotube field-effect transistors (CNTFET) technology for utilisation in an approximate multiplier. Four efficient designs for utilising the proposed compressors are introduced and analysed for a Wallace multiplier. All of the proposed circuits are analysed in 32 nm CNTFET Stanford technology and are simulated by HSPICE. In addition, as an image processing application of approximate multipliers, this paper compares the quality metrics of the image multiplication for the proposed designs and previously presented approximated multipliers. For example, the proposed schemes provide excellent results in structural similarity index up to 99%, and peak signal-to-noise ratio more than 45 dB. Also, it uses figure of metric (FOM) that includes the accuracy and quality metrics of the approximate multipliers. The simulation results demonstrate the efficiency of proposed designs.

Discrete Domain Design Scheme of Complex-Vector Current Controller for Induction Motor at Low Switching Frequency

The synchronous coordinates complex-vector proportional–integral (PI) controller is a high-performance current controller for vector-controlled ac motors, which is designed based on the continuous domain motor models. However, the application of digital signal processors in motor control necessitates the conversion of continuous domain models to discrete domain models. Moreover, the digital control itself has delay effects. Therefore, the original performance of continuous-domain-designed current controllers may be degraded. In order to improve the deteriorative performance, this article proposes corresponding delay compensation schemes for the forward Euler, backward Euler, and trapezoidal method discretized complex-vector PI controllers, respectively, which are analyzed based on discrete domain models. The root locus, frequency characteristics, and bandwidth are utilized to evaluate the performance of these three discretized controllers at the low switching frequency. Finally, the simulation and experimental results validate the analysis and the delay compensation methods proposed in this article.

An optimisation framework for the development of explicit discrete forward and inverse filters

Discrete filters are used in numerous digital signal processing applications and numerical simulations, for anti-aliasing, de-noising, and post-processing. Our specific interest is for application in large-eddy simulations. In this work, we investigate analytically the reconstruction properties of different filters, and how their discrete approximations using different rules affect the convergence and accuracy of the reconstructed signal. Following this analysis, a constrained and adaptive optimisation framework is proposed for the automated calculation of explicit forward but also direct-inverse discrete filter coefficients for a given filter transfer function. The optimised forward filters are shown to perform well with stable reconstruction using classic van Cittert iterations. The optimised direct-inverse filters eliminate the need to apply any iterations thereby substantially reducing the computational cost required for reconstruction which is one of the main challenges associated with deconvolution-based modelling in large-eddy simulations.

Design and Analysis of High Speed Multiply and Accumulation Unit for Digital Signal Processing Applications

Unit for Digital Signal Processing Applications&#x0D; &#x0D; Kausar Jahan1, Pala Kalyani2, V Satya Sai3, GRK Prasad4, Syed Inthiyaz5, Sk Hasane Ahammad6&#x0D; 1Department of ECE, Dadi Institute of Engineering and Technology&#x0D; Anakapalle, Andhra Pradesh, India&#x0D; 2Department of ECE, Vardhaman College of Engineering&#x0D; Kacharam, Shamshabad, India&#x0D; 3Department of ECE, Koneru Lakshmaiah Education Foundation&#x0D; Guntur, India-522502&#x0D; 4Department of ECE, Koneru Lakshmaiah Education Foundation&#x0D; Guntur, India-522502&#x0D; 5Department of ECE, Koneru Lakshmaiah Education Foundation&#x0D; Guntur, India-522502&#x0D; 6Department of ECE, Koneru Lakshmaiah Education Foundation&#x0D; Guntur, India-522502&#x0D; &#x0D; Abstract—The fundamental component used in many of the Digital signal Processing (DSP) applications are Multiply and Accumulation Unit (MAC). In the literature, a multiplier consists of greater number of full adders and half adder in partial product reduction stage, which increases the hardware complexity and critical path delay to MAC unit. To overcome this problem, two novel multipliers are proposed in this article. The proposed multipliers are designed and implemented in hardware, which reduces the circuit complexity and improves the overall performance of the MAC unit with less delay. The proposed multipliers are compared with the 4-bit existing designs and observed that the number of slices Look Up Tables (LUTs) are minimized from 113 to 43, Slices are reduced from 46 to 14, Full Adders (FAs) are lessened from 28 to 23, bonded Input Output Blocks (IOBs) and Half Adders (HAs) were not altered. The time delay is reduced from 14.251ns to 7.876ns. The proposed multipliers are compared in the literature with the 8-bit multiplier, then the number of Slice LUTs are reduced from 510 to 231, Slices are reduced from 218 to 113, FAs are reduced from 120 to 110, HAs are reduced from 56 to 39, time delay is reduced from 26.228ns to12.748ns, but bonded IOBs count remains same. The synthesis and simulations results are verified by using Xilinx ISE 14.7 version tool.