Application-specific Platforms Research Articles

LUT & ATIM STUDY IN IMAGE PROCESSING TECHNIQUES

For real-time inspection of color, the LUT approach is the best of the techniques considered. In computer science, a lookup table is an array that replaces runtime computation with a simpler array indexing operation. The savings in terms of processing time can be significant, since retrieving a value from memory is often faster than undergoing an expensive computation or input & output operation. The tables may be precalculated and stored in static program storage, as part of a program's initialization phase, or even stored in hardware in application-specific platforms. Lookup tables are also used extensively to validate input values by matching against a list of valid items in an array and, in some programming languages, may include pointer functions to process the matching input. The disadvantage of the LUT approach is the large memory size. The memory size has been reduced significantly by applying a multitude of ROM compression methods.

Allocating One Common ACC-Rich Platform for Many Streaming Applications

Many demanding streaming applications share functional and structural similarities with other apps in their respective domain, e.g., video analytics, software-defined radio, and radar. This opens the opportunity for specialization (e.g., heterogeneous computing) to achieve the needed efficiency and/or performance. However, current design space exploration (DSE) focuses on an individual application in isolation (e.g., one particular vision flow), but not a set of similar applications. Hence, optimizations that occur due to considering multiple applications simultaneously are missed. New DSE methodologies and tools are needed with a broader scope of application sets instead of individual applications. This article introduces a novel domain-specific DSE (DS-DSE) approach focusing on streaming applications. Key contributions are: 1) a formalized method to extract the functional and structural similarities of domain applications; 2) a rapid platform performance estimation and comparison at two abstraction levels: domain score (DS) and analytic performance estimation (APE) model; 3) two novel algorithms, dynamic score selection (DSS), and GenetIc domain exploration (GIDE), for hardware/software partitioning of a domain-specific platform to maximize the throughput across domain applications (under certain constraints); and 4) a methodology to evaluate a platform’s benefit for a set of applications. We demonstrate DSS’s and GIDE’s benefits using OpenVX applications and synthetic domains. The DSS and GIDE generated domain-specific platforms improve performance over application-specific platforms by 58% and 75% for OpenVX, as well as by 23% and 48% for synthetic applications. GIDE’s platforms reach 99.8% (OpenVX) and 97.6% (synthetic) throughput of the domain optimal platform obtained through exhaustive search.

A design flow for an optimized congestion-aware application-specific wireless network-on-chip architecture

Abstract Wireless Networks-on-Chip (WiNoC) architecture has emerged as an alternative communication infrastructure for the conventional wire-line NoC to achieve higher performance and low energy dissipation in on-chip communications. However, as realistic applications have different communication requirements, application-specific platforms are attractive to guarantee a specific level of performance. Moreover, the congestion probability over wireless routers is high, because each wireless router is shared by a group of cores. Therefore, we propose a novel methodology for designing an optimized congestion-aware application-specific WiNoC architecture. This methodology utilizes a novel mesh-of-tree (MoT) topology as a communication infrastructure to exploit the benefits of both mesh and tree topologies. Then, for a given application, the long-distance wire/wireless links are inserted into the MoT topology by considering the optimization of system cost and performance simultaneously. Furthermore, a congestion-aware layered routing is presented to reduce the congestion probability. Through cycle-accurate simulations, the performance of the proposed architecture has been evaluated and compared with state-of-the-art works under both synthetic and realistic traffic patterns in terms of network throughput, latency, and energy consumption. Moreover, the area overhead associated with the proposed WiNoC architecture is investigated. The experimental results confirmed that the proposed MoT-based WiNoC architecture is a very competitive architecture among the alternative WiNoC architectures.

DYSSS: A Dynamic and Context-Aware Security System for Shared Sensor Networks

In recent years, we have witnessed the emergence of Shared Sensor Networks (SSNs) as a core component of cyber-physical systems for diverse applications. As Wireless Sensor and Actuator Networks (WSANs) design starts shifting from application-specific platforms to shared system infrastructures, a pressing research challenge is security. In scenarios involving unprotected hostile outdoor areas, SSNs are prone to different types of attacks that can compromise reliability, integrity, and availability of the sensor data traffic and sensor lifetime as well. In this work we propose a Dynamic Security System to be applied in the shared sensor network context. Its basic feature is the nodes neighborhood monitoring and collaboration (through the use of the Byzantine algorithm) to identify an attack and enhance security. The proposed security system is dynamic since it is able to manage the availability, integrity, and confidentiality of multiple applications according to the current execution context. It is also resilient, since it is able to support the continuous network operation even in the presence of malicious or faulty nodes. Its resilience is achieved for the capacity of gathering information from several nodes, thus inferring the countermeasures using context information.

Design and implementation of application‐specific instruction‐set processor design for high‐throughput multi‐standard wireless orthogonal frequency division multiplexing baseband processor

The two implementation choices for the baseband part of wireless radios are the application-specific platforms (e.g. application-specific integrated circuits (ASICs)) and the programmable processors (e.g. digital signal processors (DSPs)). An application-specific instruction-set processor (ASIP) is a customised processor that bridges the gap between the two platforms. In this work, a novel implementation of the signal processing part of an orthogonal frequency division multiplexing (OFDM) baseband processor using three ASIPs is presented. The ASIPs provide novel architectures for the symbol chain, including fast Fourier transform, channel estimation subsystem and synchronisation subsystem. This design provides a close to DSPs level of flexibility, making it suitable for supporting all the modes of a large number of OFDM standards. In the meantime, the system maintains a performance level comparable to ASICs. This is demonstrated by providing post-layout results for 0.13 μm Taiwan semiconductor manufacturing company complementary metal-oxide semiconductor technology.

Pol

Developing applications that use complex platforms for functionalities such as authentication and messaging is hard. Model-driven engineering promises to help, but transformation systems are themselves hard to produce. We contribute a new approach using constraint-based synthesis of partial code frameworks that developers complete by hand without the need for hand-coded transformation systems . Rather, synthesis is driven by formal, partial specifications of target platforms and application architectures, and by design (code) fragments encoding application-specific platform us-age patterns. We present results of an early evaluation using the case study method to test hypotheses of feasibility and potential industrial utility, using a laboratory model of a nationwide health information network as a subject system.

The design of dynamically reconfigurable datapath coprocessors

Increasing nonrecurring engineering and mask costs are making it harder to turn to hardwired application specific integrated circuit (ASIC) solutions for high-performance applications. The volume required to amortize these high costs has been increasing, making it increasingly expensive to afford ASIC solutions for medium-volume products. This has led to designers seeking programmable solutions of varying sorts using these so-called programmable platforms. These programmable platforms span a large range from bit-level programmable field programmable gate arrays to word-level programmable application-specific, and in some cases even general-purpose processors. The programmability comes with a power and performance overhead. Attempts to reduce this overhead typically involve making some core hardwired ASIC like logic blocks accessible to the programmable elements. This paper presents one such hybrid solution in this space---a relatively simple processor with a dynamically reconfigurable datapath acting as an accelerating coprocessor. This datapath consists of hardwired function units and reconfigurable interconnect. We present a methodology for the design of these solutions and illustrate it with two complete case studies: an MPEG2 coder, and a GSM coder, to show how significant speedups can be obtained using relatively little hardware. This work is part of the MESCAL project, which is geared towards developing design environments for the development of application-specific platforms.