Application Specific Integrated Circuit Technology Research Articles

Performance Evaluation of the uMI Panorama PET/CT System in Accordance with the National Electrical Manufacturers Association NU 2-2018 Standard.

The uMI Panorama is a novel PET/CT system using silicon photomultiplier and application-specific integrated circuit technologies and providing exceptional spatial and time-of-flight (TOF) resolutions. The objective of this study was to assess the physical performance of the uMI Panorama in accordance with the National Electrical Manufacturers Association (NEMA) NU 2-2018 standard. Methods: Spatial resolution, sensitivity, count rate performance, accuracy, image quality, and TOF resolution were evaluated in accordance with the guidelines outlined in the NEMA NU 2-2018 standard. Energy resolution was determined using the same dataset acquired for the count rate performance evaluation. Images from a Hoffman brain phantom, a mini-Derenzo phantom, and 3 patient studies were evaluated to demonstrate system performance. Results: The transaxial spatial resolution at full width at half maximum was measured as 2.88 mm with a 1-cm offset from the center axial field of view. The sensitivity at the center axial field of view was 20.1 kcps/MBq. At an activity concentration of 73.0 kBq/mL, the peak noise-equivalent count rate (NECR) reached 576 kcps with a scatter fraction of approximately 33.2%. For activity concentrations at or below the peak NECR, the maximum relative count rate error among all slices remained consistently below 3%. When assessed using the NEMA image quality phantom, overall image contrast recovery ranged from 63.2% to 88.4%, whereas background variability ranged from 4.2% to 1.1%. TOF resolution was 189 ps at 5.3 kBq/mL and was consistently lower than 200 ps for activity concentrations at or below the peak NECR. The patient studies demonstrated that scans at 2 min/bed produced images characterized by low noise and high contrast. Clear delineation of nuclei, spinal cords, and other substructures of the brain was observed in the brain PET images. Conclusion: uMI Panorama, the world's first commercial PET system with sub-200-ps TOF resolution, demonstrated fine spatial and fast TOF resolutions, robust count rate performance, and high quantification accuracy across a wide range of activity levels. This advanced technology offers enhanced diagnostic capability for detecting small and low-contrast lesions while showing promising potential under high-count-rate imaging scenarios.

Design, integration and implementation of crypto cores in an SoC environment

PurposeThe paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.Design/methodology/approachAn integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.FindingsFPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.Originality/valueThe proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

Evaluation and characterization of approximate arithmetic circuits

SummaryWith the end of Dennard's scale, processor designers have been looking for new technical alternatives so that approximate computing (AC) has managed to attract the attention of researchers by offering techniques ranging from the application level to the circuit level. When applying approximate circuits into hardware design, the program user may speed up the application. At the same time, a designer may save area and power dissipation at the cost of less accuracy on the results of operations. This article discusses the compromise between controlled accuracy versus physical efficiency by evaluating a set of arithmetic circuits designs. The article also presents new mixed organization approximate designs. To evaluate the approximate design benefits, we performed a comprehensive set of experiments from tailor‐made approximate arithmetic circuits on field‐programmable gate array and application specific integrated circuits technologies. Our results reveal that our proposed mixed approximate designs have promising results on error rates, area usage, and power dissipation compared to the related work. Another interesting result is that one should care about the prototyping platform where the approximate hardware will be synthesized. Tailor‐made approximate cells may take advantage on intrinsic design details than standard cells or even general prototyping platforms.

Hardware architecture for real-time EEG-based functional brain connectivity parameter extraction

Objective. Design a novel architecture for real-time quantitative characterization of functional brain connectivity (FC) networks derived from wearable electroencephalogram (EEG). Approach. We performed an algorithm to architecture mapping for the calculation of phase lag index to form the functional connectivity networks and the extraction of a set of graph-theoretic parameters to quantitatively characterize these networks. This mapping was optimized using approximations in the mathematical definitions of the algorithms which reduce its computational complexity and produce a more hardware amenable implementation. Main results. The architecture was developed for a 19-channel EEG system. The system can calculate all the functional connectivity parameters in a total time of 131 µs, utilizes 71% of the total logic resources in the FPGA, and shows 51.84 mW dynamic power consumption at 22.16 MHz operation frequency when implemented in a Stratix IV EP4SGX230K FPGA. Our analysis also showed that the system occupies an area equivalent to approximately 937 K 2-input NAND gates, with an estimated power consumption of 39.3 mW at 0.9 V supply using a 90 nm CMOS application specific integrated circuit technology. Significance. The proposed architecture can calculate the FC and extract the graph-theoretic parameters in real-time with low power consumption. This characteristic makes the architecture ideal for applications such as a wearable closed-loop neurofeedback systems, where constant monitoring of the brain activity and fast processing of EEG is necessary to control the appropriate feedback.

Novel multiplex capacitive sensor based on molecularly imprinted polymers: A promising tool for tracing specific amphetamine synthesis markers in sewage water

The development of a sensing system for amphetamine (AMP), N-formyl amphetamine (NFA), and benzyl methyl ketone (BMK) in sewage is a strict requirement for enabling the on-site detection and tracing of the consumption of AMP, and the production and/or transportation of these target analytes. The present research is therefore devoted to the development of an on-site capacitive sensing system, based on molecularly imprinted polymers (MIPs) as recognition elements.To this end, the commercially available CapSenze capacitive sensor system was miniaturized by implementing an application-specific integrated circuit (ASIC), dedicated to the bias and read-out of the chemical sensor. MIPs towards AMP were purchased, whereas the ones towards NFA and BMK were synthesized in house. Gold transducers, consisting of six working electrodes with their corresponding reference electrodes and one common auxiliary electrode, were designed together with a flow cell to enable analyses. The applied water samples were filtered through a 20 micron filter before application in the sensors’ flow cell. The limits of detection in filtered sewage water were determined to be 25 μM for NFA and BMK and 50 μM for AMP. The overall performance of the sensing system was tested by analysis of blind-coded sewage samples, provided by legal authorities.To the best of our knowledge, this is the first research presenting multiplex MIP-based detection of amphetamine synthesis markers using a capacitive sensor, miniaturized via ASIC technology. The presented technique is undoubtedly a potential solution for any analysis requiring constant reliable on-site monitoring of a substance of interest.

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme

Reversible logic has been emerging as a replacement for conventional digital computers and has been found to be a promising technology for the future that can improve the quality of circuits in terms of power, speed, heat dissipation, life span, and input traceability. The new generation of quantum processors demands the efficient implementation of decimal data path elements in many commercial, financial, and Internet-based applications. Reversible binary-coded decimal multipliers are among the important circuits in quantum computers. In this approach, we propose a low-power reversible radix binary-coded decimal multiplier. The proposed methodology uses a novel 4221 reversible recorder gate to select precomputed constant multiples and binary to excess-six conversion reversible decimal adder for partial product compression. The proposed multiplier is designed with 180-nm application-specific integrated circuit technology using the Cadence EDA tool and is compared with state-of-the-art BCD algorithms designed using reversible gates. Experimental evaluations revealed that the proposed design demonstrates power and power-delay product reductions of 28% and 37%, respectively, compared to those of the best BCD algorithms implemented in reversible logic.

An efficient hardware implementation of the elliptic curve cryptographic processor over prime field,

SummaryElliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest‐Shamir‐Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, . This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex‐7 FPGA platform over 224‐bit and 256‐bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal‐oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field and , respectively. This design provides better area‐delay product and high throughput value in both FPGA and ASIC when compared with other designs.

SiGe Integrated Circuit Developments for SQUID/TES Readout

SiGe integrated circuits dedicated to the readout of superconducting bolometer arrays for astrophysics have been developed since more than 10 years at APC. Whether for Cosmic Microwave Background (CMB) observations with the QUBIC ground-based experiment (Aumont et al. in astro-ph.IM, 2016. arXiv:1609.04372 ) or for the Hot and Energetic Universe science theme with the X-IFU instrument on-board of the ATHENA space mission (Barret et al. in SPIE 9905, space telescopes & instrumentation 2016: UV to $$\gamma $$ Ray, 2016. https://doi.org/10.1117/12.2232432 ), several kinds of Transition Edge Sensor (TES) (Irwin and Hilton, in ENSS (ed) Cryogenic particle detection, Springer, Berlin, 2005) arrays have been investigated. To readout such superconducting detector arrays, we use time or frequency domain multiplexers (TDM, FDM) (Prele in JINST 10:C08015, 2016. https://doi.org/10.1088/1748-0221/10/08/C08015 ) with Superconducting QUantum Interference Devices (SQUID). In addition to the SQUID devices, low-noise biasing and amplification are needed. These last functions can be obtained by using BiCMOS SiGe technology in an Application Specific Integrated Circuit (ASIC). ASIC technology allows integration of highly optimised circuits specifically designed for a unique application. Moreover, we could reach very low-noise and wide band amplification using SiGe bipolar transistor either at room or cryogenic temperatures (Cressler in J Phys IV 04(C6):C6-101, 1994. https://doi.org/10.1051/jp4:1994616 ). This paper discusses the use of SiGe integrated circuits for SQUID/TES readout and gives an update of the last developments dedicated to the QUBIC telescope and to the X-IFU instrument. Both ASIC called SQmux128 and AwaXe are described showing the interest of such SiGe technology for SQUID multiplexer controls.

ASIC chipset design to generate block-based complex holographic video.

In this paper, we propose a new hardware architecture implemented as a very large scaled integrated circuit by using an application-specific integrated circuit technology, where block-based calculations are used to generate holograms. The proposed hardware is structured to produce a part of a hologram in the block units in parallel. A block of a hologram is calculated using an object point, and then the calculation is repeated for all object points to obtain intermediate results that are accumulated to produce the final block of a hologram. This structure can be used to produce holograms of various sizes in real time with optimized memory access. The proposed hardware was implemented using the Hynix 0.18 μm CMOS technology of Magna Chip, Inc., and it has about 448 K gate counts and a silicon size of 3.592 mm×3.592 mm. It can generate complex holograms and operate in a stable manner at a clock frequency of 200 MHz.

Cost-Efficient Integration of Industrial Applications Using Smart Power Gate Arrays

Due to high functional variety, wide power rating range, and relatively low product volumes, electronic systems for industrial application are difficult to economically be integrated on a chip. This paper presents the smart power gate array (SPGA), a novel application-specific integrated circuit (ASIC) platform exactly aimed at enabling cost-efficient single-chip integration of industrial electronic systems. The SPGA combines a low-voltage mixed-signal gate array with a structured high-voltage smart-power core, allowing for single-chip integration of signal conditioning, data processing, power management, actuator driving, and line communication functionalities required for industrial applications. Simultaneously, it offers low nonrecurring engineering cost and high design flexibility owning to the utilized gate array technology. In this paper, the SPGA concept is introduced to overcome integration limitations of existing ASIC technologies. Then, design and capabilities of the SPGA functional modules are described. Finally, a practical SPGA application example of single-chip integrated solenoid valve control and monitoring system is demonstrated.

Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators

The computing demand of many signal processing algorithms is dramatically growing because of the increasing complexity of embedded software applications. Concurrently, as process technology scales, the design effort for realizing very large scale integrated circuits and the associated costs are becoming critically high. A possible solution to address this performance/costs challenge is given by customizable multiprocessor system-on-chips. The approach proposed in this paper leads to the customization of multi/many processor system-on-chip at two levels of abstraction: 1) customization through application-specific hardware accelerators implemented on configurable datapath that can target three kinds of structured application-specific integrated circuit technologies: metal, via, and runtime programmable and 2) customization of the architectural parameters of the platform. The proposed platform is equipped with a design framework that assists the user in the high-level design-space exploration of signal processing applications described using the Open Computing Language (OpenCL) language. A peculiar added value of the flow is to support the migration of OpenCL kernels and tasks into pipelined hardware accelerators described using a C-level language. The platform is able to provide an average performance of 90 GOPS on a set of reference signal processing applications, and an average computational energy efficiency of 130 GOPS/W in its metal-programmable configuration. This result shows the benefits in terms of energy efficiency of hardware customization applied to multiprocessor systems with respect to many core devices such as general-purpose graphic processing units, able to provide on average 2.5 GOPS/W for the applications under analysis.

Scalable design of microprogrammed digital FIR filter for sensor processing subsystem

In this letter, a novel scalable and modular design of direct form sequential finite impulse response (FIR) filter using microprogrammed control unit is proposed that can be efficiently realized in field programmable gate array (FPGA) or application specific integrated circuit (ASIC). The proposed design is suitable for sensor processing subsystem used in wireless sensor network (WSN) nodes. This is demonstrated by evaluating a sample 4-tap FIR filter on various FPGA platforms and ASIC technologies. The evaluation result shows good area/power efficiency and flexibility by using microprogrammed architecture for such applications.

Design of an ASIC Chip for Spacecraft Data System

ASIC (Application Specific Integrated Circuit) technology is mature and widely used in many fields. It is a trend to integrate some common spacecraft engineering requirements into one chip to take the place of FPGA and some digital chips, which can miniaturize spacecraft avionics and reduce the repeated work for spacecraft engineers. Based on the analysis on small satellites application requirements, the system design of an ASIC chip for spacecraft data system is proposed. Firstly, the chip system architecture is described. Secondly, four key technologies of the ASIC chip design are presented in detail. They are the design of the chip's operating modes, the design of IP cores, the design of reliability, and the design of low power consumption. Generality, adaptability and independent intellectual property make this ASIC different and special from other space chips. Four operating modes are optional: 1553B bus control mode, PCI control mode, ISA control mode, internal CPU control mode. Besides, there are 1553B bus protocol IP cores, CAN bus interface, and abundant peripherals, which can satisfy most of the routine engineering requirements in small satellites. Finally, the chips status and some promising applications are described.

Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains

In this paper, we introduce a source-synchronous adaptive interface for the globally ratiochronous, locally synchronous design style, a subset of the globally asynchronous, locally synchronous (GALS) design style in which the frequencies of all clocks are not phase-aligned but are constrained to be rationally related, i.e., they are all submultiple of the same physical or virtual frequency. The interface can be designed using only standard cells and guarantees maximal throughput in addition to an average latency four times lower compared with state-of-the-art asynchronous first-input, first-output GALS interfaces. Several properties of the interface are formally stated and proved. We also demonstrate that the interface has a low area overhead, with only four flip-flops per data line, and is robust against nonidealities such as clock jitters and propagation delay misalignments. For a realistic link in 90-nm application-specific integrated circuit technology, we derive a 1-GHz upper bound for the least common multiple among the frequencies.

Clock, Flip-Flop, and Combinatorial Logic Contributions to the SEU Cross Section in 90 nm ASIC Technology

Utilizing an application specific integrated circuit (ASIC) with 140 different shift chains, and a wide variety of test modes, a design of experiments (DOE) approach was used to characterize a commercial 90 nm CMOS technology for its sensitivity to single event effects (SEE). The variables characterized included: well structure on the wafer, density of well contacts, logic data pattern, angle of indicence, flip-flop redundancy, variation in sensitive node spacing, and the effect of transients as a function of combinatorial logic type. Analysis of the cross section contribution from the clock, flip-flop and SET target circuitry showed that any hardening technique used in a production integrated circuit may be limited in its effectiveness due to other circuits and logic in the integrated circuit.

Optimal estimation of the relevant information coming from a variable reluctance proximity sensor placed in a car undergoing performance tests

Today's automotive industry has a soaring interest in efficient, reliable and robust sensors able to make intelligent driving decisions that can save millions of lives every year. To that end, the sensors used in today's cars are being provided with microprocessors and application-specific integrated circuit technologies that incorporate a certain amount of intelligence into the sensors themselves. In this paper, an inverse square-root adaptive filtering algorithm for recursive least-squares estimation (QR-RLS) is used to improve the response of a wheel speed sensor placed in a car undergoing performance tests. Such an algorithm is used to carry out an optimal estimation of the relevant signal coming from the sensor, which is buried in a broad-band noise background where we have little knowledge of the noise characteristics. The results of the experiment are satisfactory, a significant improvement of 32.5 dB in the signal-to-noise ratio at the QR-RLS adaptive filter output was achieved. Also, in order to compare classical filtering techniques with optimal adaptive filtering techniques, the signal coming from the wheel speed sensor was also filtered by using a second-order lowpass digital Butterworth filter. The results of comparing the aforementioned filters show that the optimal adaptive filter is superior to the classical filter.

FPGA vs. ASIC for low power applications

Field Programmable Gate Array (FPGA) are becoming more and more popular and are used in many applications. However, it is well known that the performance is limited comparing to full ASIC implementation, but for many applications the speed requirements fit the ones provided already by existing FPGA circuits. Power consumption seems to be one of the most important limiting factor and so far it is in favour of Application Specific Integrated Circuits (ASIC) [Varghese Georges, Jan M. Rabaey, Low-Energy FPGA, Architecture and Design, Kluwer Academic Publishers, 2001; Tadahiro Kuroda, Power-Aware Electronics: Challenges and Opportunities, Tutorial at FTFC 2003, Paris, May 2003]. In this paper, we will present results obtained by characterizing various circuits implemented using both FPGA and ASIC technologies in order to determine the power consumption ratio and evaluate the efficiency of the power optimization techniques such as clock gating [Amara AMARA, Philippe Royannez, VHDL for Low Power, (Chapter 11), Low Power Electronics Design, Edited by Christian Piguet, CRC Press 2005; Luca Benini, Giovanni De Micheli, Dynamic Power Management, Kluwer Academic Publishers, 1998]. We have started a study in order to compare the power consumption of two Intellectual Property (IP), a counter circuit and an image transform circuit. Both circuits have been implemented using FPGA Family circuits from ALTERA and Hardware Copy of the circuits which are close to the ASIC implementation. A full ASIC implementation using UMC 0.13 μm have be also characterized in terms of power. FPGA power consumption estimation flow is based on ALTERA tools (QuartusII) that provide accurate overall power consumption for a set of input stimuli, on various targets: FPGA families and Hardware Copy. ASIC power consumption estimation flow is based on Synopsys Power tools.

Area efficient FIR filters for high speed FPGA implementation

A new algorithm that synthesises multiplier blocks with low hardware requirement suitable for implementation as part of full-parallel finite impulse response (FIR) filters is presented. Although the techniques in use are applicable to implementation on application-specific integrated circuit (ASIC) and Structured ASIC technologies, analysis is performed using field programmable gate array (FPGA) hardware. Fully pipelined, full-parallel transposed-form FIR filters with multiplier block were generated using the new and previous algorithms, implemented on an FPGA target and the results compared. Previous research in this field has concentrated on minimising multiplier block adder cost but the results presented here demonstrate that this optimisation goal does not minimise FPGA hardware. Minimising multiplier block logic depth and pipeline registers is shown to have the greatest influence in reducing FPGA area cost. In addition to providing lower area solutions than existing algorithms, comparisons with equivalent filters generated using the distributed arithmetic technique demonstrate further area advantages of the new algorithm.

Implementing an OFDM receiver on the RaPiD reconfigurable architecture

Field-programmable gate arrays (FPGAs) have become an extremely popular implementation technology for custom hardware because they offer a combination of low cost and very fast turnaround. Because of their in-system reconfigurability, FPGAs have also been suggested as an efficient replacement for application-specific integrated circuits (ASICs) and digital signal processors (DSPs) for applications that require a combination of high performance, low cost, and flexibility. Unfortunately, the use of FPGAs in mobile embedded systems platforms is hampered by the very large overhead of FPGA-based architectures. Coarse-grained configurable architectures can reduce this overhead substantially by taking advantage of the application domain to specialize the reconfigurable architecture via coarse-grained components and interconnects. This paper presents the design and implementation of an OFDM receiver in the RaPiD reconfigurable architecture as a case study for comparing the relative cost and performance of ASIC, DSP, FPGA, and coarse-grained reconfigurable architectures. RaPiD is a coarse-grained reconfigurable architecture specialized to the domain of signal and image processing. The RaPiD architecture provides a reconfigurable pipelined datapath controlled by efficient reconfigurable control logic: We have implemented the computationally intensive parts of an OFDM receiver on the RaPiD architecture and have developed careful estimates of corresponding implementations in representative ASIC, DSP and FPGA technology. Our results show that, for this application, RaPiD fills the cost/performance gap between programmable DSP and ASIC architectures, achieving a factor of 6 better than a DSP implementation but a factor of 6 less than an ASIC implementation.